Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.

Abstract: A method for forming a cavity in a silicon substrate, a surface of the silicon substrate having a tilting angle relative to a first plane of the silicon substrate, and the first plane being a {111} plane of the silicon substrate, and situation of an etching mask on the surface of the silicon substrate. The etching mask has a retarding structure that protrudes into the mask opening, and a first etching projection region. All further edges of the mask opening outside the first etching projection region are situated essentially parallel to {111} planes of the silicon substrate. The method includes an anisotropic etching of the silicon substrate during a defined etching duration. An etching rate in the <111> directions of the silicon substrate is lower than in other spatial directions, and the first retarding structure is undercut in a first undercut direction going out from the first etching projection region.

Abstract: The present disclosure provides a method for manufacturing a conductive line. The method includes steps of providing a substrate; forming a metal layer on the substrate; patterning the metal layer by etching a portion of the metal layer; and performing a post-treatment process on the patterned metal layer in a chamber by injecting a CxHyFz gas and water vapor into the chamber, such that the patterned metal layer avoids from being corroded after the post-treatment process is performed.

Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Abstract: A display apparatus including a display substrate, a light-emitting device on the display substrate, an encapsulation substrate on the light-emitting device and bonded to the display substrate, and a diffraction-grating layer on a top surface of the encapsulation substrate, wherein the diffraction-grating layer includes a plurality of diffraction patterns spaced apart from one another by a predetermined distance, and each of the plurality of diffraction patterns has a stacked structure of a lower layer and an upper layer, wherein the lower and upper layers include different materials.

Abstract: The present invention provides a method for improving the quality of a high-voltage metal oxide semiconductor (HV MOS), the method includes: firstly, a substrate is provided, next, a hard mask layer is formed on the substrate, an oxygen plasma treatment is then performed to the hard mask layer, so as to form an oxide layer on the hard mask layer. Afterwards, a patterned photoresist layer is formed on the oxide layer, and a first cleaning process is performed to a top surface of the oxide layer after the patterned photoresist layer is formed, wherein the first cleaning process comprises rinsing the oxide layer with carbonated water. Next, a first etching process is performed to remove parts of the hard mask layer, and the patterned photoresist layer is then removed. Afterwards, a second etching process is performed, to remove the oxide layer.

Abstract: An optoelectronic device and a method are disclosed.

Abstract: Systems, methods, and other embodiments are disclosed for validating measured meter data. In one embodiment, a graphical user interface is provided that facilitates configuration of a validation algorithm by a user. Historical usage data is accessed during a non-peak time to offload processing from a peak time. The non-peak time corresponds to a time span when the measured meter data is not being received and/or is not being validated, and the peak time corresponds to a different time span when the measured meter data is being validated. Statistical data is generated from the historical usage data during the non-peak time and stored in a memory. The measured meter data is received and the statistical data is accessed during the peak time. The measured meter data is validated by applying the validation algorithm to the statistical data and the measured meter data during the peak time.

Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, and a first semiconductor layer over the substrate. At least a portion of the first semiconductor layer is surrounded by the isolation structure. The semiconductor device further includes a doped material layer between the isolation structure and the first semiconductor layer.

Abstract: Certain embodiments may generally relate to a smart fault detection device for power grids, and a method of fault detection for power grids. A method may include receiving raw data samples of currents in grounding conductors and line conductors. The method may also include processing the raw data samples under at least one of a plurality of system operating modes. The method may also include monitoring normal operation and anticipating an impending fault while operating under at least one of the system operating modes. The method may further include extracting fault information based on the monitoring. The method may also include reporting the fault information to a supervisory control and data acquisition system human-machine interface. The method may further include anticipating faults based on an analysis of the raw data samples.

Abstract: An integrated circuit package element provided includes a chip element and a package module coupled to the chip element. The chip element includes two driving units that are electrically connected to each other. The package module includes a grounding area, two individual power distributed networks and a grounded shielding structure which is completely disposed between the individual power distributed networks, electrically connected to the chip element, and configured to block power noise coupling between the first electric power distribution network and the second electric power distribution network. The grounding area is electrically connected to the individual electric power distribution networks and the grounded shielding structure.

Abstract: A method is provided for fabricating a graphene light emitting transistor. The method includes: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate and the gate electrode; forming a graphene oxide layer on the gate insulating layer; reducing two ends of the graphene oxide layer to respectively form a source electrode and a drain electrode made of graphene; forming a graphene quantum dot layer on an unreduced part of the graphene oxide layer, the source electrode, and the drain electrode; and forming a water and oxygen resistant layer on the graphene quantum dot layer.

Abstract: Aspects of the present disclosure include a semiconductor structure comprising a gate layer with an associated gate dielectric thereon, and a region comprising at least one fin structure in contact with the gate layer, wherein the fin structure includes at least two distinct materials, and wherein one of the two distinct materials is a Zn based material.

Abstract: A flip chip package includes a substrate, a chip body bonding on the substrate and bumps connected between the chip body and the substrate. The substrate includes input wires and output wires. The chip body includes a first package unit including a first seal ring and first pads and a second package unit including a second seal ring and second pads. The chip body extends continuously between the first seal ring and the second seal ring. Each of the input wires has one end overlapping the chip body and the other end positioned at a first bonding region of the substrate. Each of the output wires has one end overlapping the chip body and the other end positioned at a second bonding region of the substrate. The first bonding region and the second bonding region are located at opposite sides of the chip body.

Abstract: To provide an imaging device that is able to have both excellent pixel characteristics and a great power generation amount. An imaging device according to an embodiment of the present disclosure includes: a semiconductor substrate that includes one surface to be a light entering surface and another surface opposed to the one surface; an imaging unit that is provided in the semiconductor substrate and includes a plurality of sensor pixels that performs photoelectric conversion; and an electric power generating unit that is provided around the imaging unit of the semiconductor substrate and performs photoelectric conversion.

Abstract: A method for manufacturing a photoelectric converter includes a first step of preparing a semiconductor substrate including a metal oxide semiconductor (MOS) transistor, a second step of forming a plurality of interlayer insulating films above the semiconductor substrate, and a third step of forming a photoelectric conversion portion above the semiconductor substrate. The second step includes a step of forming a first film containing hydrogen. The third step includes a step of forming a first electrode, a step of forming a photoelectric conversion film, and a step of forming a second electrode. The method includes a step of performing heat treatment between the step of forming the first film and the step of forming the photoelectric conversion film.

Abstract: A semiconductor structure includes a semiconductor mesa situated on a semiconductor substrate, a trap-rich region comprising polycrystalline silicon adjacent to the semiconductor mesa, and a phase-change material (PCM) radio frequency (RF) switch. A heating element of the PCM RF switch is situated over the semiconductor mesa. An interconnect segment coupled to the PCM RF switch is situated over the trap-rich region. Alternatively, a semiconductor structure can include a trap-rich region adjacent to a single crystal region of the semiconductor substrate, where the trap-rich region is formed by implant damaging, and where the heating element of the PCM RF switch is situated over the single crystal region.

Abstract: In a method for wafer-to-wafer bonding, an integrated circuit (IC) wafer and a phase-change material (PCM) switch wafer are provided. The IC includes at least one active device, and has an IC substrate side and a metallization side. The PCM switch wafer has a heat spreading side and a radio frequency (RF) terminal side. A heat spreader is formed in the PCM switch wafer. In one approach, the heat spreading side of the PCM switch wafer is bonded to the metallization side of the IC wafer, then a heating element is formed between the heat spreader and a PCM in the PCM switch wafer. In another approach, a heating element is formed between the heat spreader and a PCM in the PCM switch wafer, then the RF terminal side of the PCM switch wafer is bonded to the metallization side of the IC wafer.

Abstract: The present disclosure relates to a semiconductor device and an electronic apparatus which is capable of reducing variations and deterioration of transistor characteristics. A first connection pad connected with a first wiring and a first floating metal greater than the first connection pad are formed at a bonding surface of a first substrate, whereas a second connection pad connected with a second wiring and a second floating metal greater than the second connection pad are formed at a bonding surface of a second substrate. The first floating metal and the second floating metal formed at the first substrate and the second substrate are bonded to each other. The present disclosure is applicable to a CMOS solid-state imaging device used for an imaging apparatus such as a camera, for example.

Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.