Abstract: An embodiment includes an apparatus comprising: a substrate; a magnetic tunnel junction (MTJ), on the substrate, comprising a fixed layer, a free layer, and a dielectric layer between the fixed and free layers; and a first synthetic anti-ferromagnetic (SAF) layer, a second SAF layer, and an intermediate layer, which includes a non-magnetic metal, between the first and second SAF layers; wherein the first SAF layer includes a Heusler alloy. Other embodiments are described herein.

Abstract: An image sensor may include a photosensing region in a substrate and configured to generate photoelectrons in response to an incident light on the photodiode region, conductive bias patterns disposed to be spaced apart from one another and surrounding the photosensing region, and pixel isolation patterns that are spaced apart from and disposed in a periphery of the conductive bias patterns.

Abstract: A display device according to the present invention includes a substrate, and a plurality of pixels arranged in the substrate, wherein each of the plurality of pixels includes a light emitting element, a first transistor, a second transistor, a first insulation layer and a second insulation layer, the first transistor includes a first semiconductor layer, the second transistor includes a second semiconductor layer, the first insulation layer is arranged across the plurality of pixels between the first semiconductor layer and the second semiconductor layer, the second insulation layer is arranged between the first insulation layer and the second semiconductor layer, the first semiconductor layer is arranged on the substrate side sandwiching the first insulation layer with respect to the second semiconductor layer, the first insulation layer includes a silicon oxide layer; and the second insulation layer includes an aluminum oxide layer.

Abstract: An image sensor may include a pixel array including different pixel blocks where a pixel block includes a block of adjacent unit pixels each unit responsive to light to produce photo-generated charges, a floating diffusion region disposed at a center of each unit pixel to receive the photo-generated charges, and transfer gates formed between the floating diffusion region and the unit pixel to control the transfer of the photo-generated charges. Each the pixel block may include an extra floating diffusion region at a center of the pixel block to interface with each of the adjacent unit pixels with the pixel block to photo-generated charges from each of the adjacent unit pixels and extra transfer gates that are formed between the extra floating diffusion region and the adjacent unit pixels to control the transfer of the photo-generated charges from the adjacent unit pixels to the extra floating diffusion region.

Abstract: An image sensor may include an antireflection layer formed over a substrate, grid patterns and a guide pattern that are disposed over the antireflection layer, a color filter between the grid patterns, a phase difference detection filter structured to include a portion between one of the grid patterns and the guide pattern, and a lining layer formed to include a portion between one of the grid patterns and the phase difference detection filter. The lining layer has a refractive index lower than that of the phase difference detection filter.

Abstract: A display device includes a first substrate layer having a first, second, and third through holes spaced apart from each other; a second substrate layer having a fourth through hole; a first intermediate conductive layer having a first exposed portion exposed through the first through hole, and a second exposed portion exposed through the second through hole; a second intermediate conductive layer having a third exposed portion exposed through the third through hole; a wiring on the second substrate layer and electrically connected to the second intermediate conductive layer through the fourth through hole; a first electronic device on the first substrate layer and electrically connected to the first exposed portion; and a second electronic device on the first substrate layer and electrically connected to the second exposed portion and the third exposed portion.

Abstract: An exemplary method includes forming a common source region in a substrate, and forming an isolation feature over the common source region. The common source region is disposed between the substrate and the isolation feature. The common source region and the isolation feature span a plurality of active regions of the substrate. A gate, such as an erase gate, may be formed after forming the common source region. In some implementations, the common source region is formed by etching the substrate to form a saw-tooth shaped recess region (or a U-shaped recess region) and performing an ion implantation process to form a doped region in a portion of the saw-tooth shaped recess region (or the U-shaped recess region), such that the common source region has a sawtooth profile (or a U-shaped profile).

Abstract: A lighting device includes a first lighting unit and a second lighting unit. The first lighting unit emits a first light spectrum having a main peak between 525 nm and 585 nm and a first sub peak between 400 nm and 470 nm. The second lighting unit emits a second light spectrum having a main peak between 595 nm and 775 nm and a second sub peak between 400 nm and 470 nm. An intensity of the first sub peak is different from an intensity of the second sub peak.

Abstract: An electromagnetic wave detector, which photoelectrically converts and detects an electromagnetic wave incident on a graphene layer, including: a substrate having a front surface and a back surface; a lower insulating layer provided on the front surface of the substrate; a ferroelectric layer and a pair of electrodes provided on the lower insulating layer, the pair of electrodes arranged to face each other with the ferroelectric layer sandwiched therebetween; an upper insulating layer provided on the ferroelectric layer; and a graphene layer arranged on the lower insulating layer and the upper insulating layer to connect the two electrodes. Alternatively, the electromagnetic wave detector includes: a graphene layer provided on the lower insulating layer; and a ferroelectric layer provided on the graphene layer with an upper insulating layer interposed therebetween and a pair of electrodes provided on the graphene layer to face each other with the ferroelectric layer sandwiched therebetween.

Abstract: A method for fabricating an interconnect for integrated circuit is described. A recess is provided in a first dielectric layer comprising a first dielectric and a second dielectric layer comprised of a second dielectric. The first and second dielectric layers are disposed over a substrate. The second dielectric layer is disposed over the first dielectric layer. The recess is filled with a metal conductor. A chemical mechanical polishing process removes the metal conductor from field areas on the second dielectric layer. The second dielectric layer is removed. An interconnect element is created having a top face which protrudes higher than a top face of the first dielectric layer. The metal conductor of the interconnect element has direct contact with the first dielectric layer. In other aspects of the invention, the interconnect structure is described.

Abstract: The invention describes a thermal block assembly comprising a first thermally and electrically conductive block part realised for connection to an anode pad of a light-emitting diode (LED) and dimensioned to provide an essentially complete thermal path for heat originating at the anode pad; a second thermally and electrically conductive block part realised for connection to a cathode pad of the LED and dimensioned to provide an essentially complete thermal path for heat originating at the cathode pad; and a bonding layer applied to the block parts to fix the positions of the block parts on either side of a gap. The invention further describes an LED arrangement comprising said thermal block assembly and at least one LED mounted thereto, and a method of manufacturing said thermal block assembly.

Abstract: An optoelectronic component is provided having a cathode, an anode and a layer system between the cathode and the anode, the layer system includes electroactive layers, in particular charge-carrier injection and transport layers, and including an optically active layer, the charge-carrier injection and transport layers themselves being a diffusion barrier to water or oxygen.

Abstract: A micro-LED module is disclosed. The micro-LED module includes a flexible circuit board and a plurality of LED pixels mounted on the flexible circuit board. Each of the plurality of LED pixels includes a first micro-LED chip, a second micro-LED chip, and a third micro-LED chip. Each of the first micro-LED chip, the second micro-LED chip, and the third micro-LED chip has at least one side whose length is 100 ?m or less. Each of the first micro-LED chip, the second micro-LED chip, and the third micro-LED chip includes one or more electrode pads having a width of 80 ?m or less on the surface facing the flexible circuit board. The flexible circuit board includes a first flexible insulating film including electrode patterns formed on the upper surface thereof and connected to the electrode pads through solder bumps having a diameter of 80 ?m or less and a second flexible insulating film connected to the bottom of the first flexible insulating film through a first conductive pattern.

Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.

Abstract: A fabricating method for a display apparatus is provided. The fabricating method for the display apparatus includes the following steps. An array substrate having a first electrode and a second electrode is provided. A first light emitting diode is heated to soften a first bump between the first electrode and the first light emitting diode, the first light emitting diode is bonded onto the first electrode by the first bump. The first light emitting diode and a second light emitting diode are heated to soften the first bump and a second bump between the second electrode and the second light emitting diode, the second light emitting diode is bonded onto the second electrode by the second bump, and the first light emitting diode and the second light emitting diode are pressed.

Abstract: A receiver optical module that receives an optical signal and generating an electrical signal corresponding to the optical signal is disclosed. The module includes a photodiode (PD), a sub-mount, a pre-amplifier, and a stem. The sub-mount, which is made of insulating material, mounts the PD thereon. The pre-amplifier, which receives the photocurrent generated by the PD, mounts the PD through the sub-mount with an adhesive. The pre-amplifier generates an electrical signal corresponding to the photocurrent and has signal pads and other pads. The stem, which mounts the pre-amplifier, provides lead terminals wire-bonded with the signal pads of the pre-amplifier. The signal pads make distances against the sub-mount that are greater than distances from the other pads to the sub-mount.

Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. The photodiode comprises a doped layer with a first doping type and an adjoining region of the substrate with a second doping type that is different than the first doping type. A boundary deep trench isolation (BDTI) structure is disposed between adjacent pixel regions. A multiple deep trench isolation (MDTI) structure overlies the doped layer of the photodiode. The MDTI structure comprises a stack of dielectric layers lining sidewalls of a MDTI trench. A plurality of color filters is disposed at the back-side of the substrate corresponding to the respective photodiode of the plurality of pixel regions and overlying the MDTI structure.

Abstract: A resistive element includes: a semiconductor substrate; a first insulating film deposited on the semiconductor substrate; a resistive layer deposited on the first insulating film; a second insulating film deposited to cover the first insulating film and the resistive layer; a first electrode deposited on the second insulating film and electrically connected to the resistive layer; a relay wire deposited on the second insulating film without being in contact with the first electrode, and including a resistive-layer connection terminal electrically connected to the resistive layer and a substrate connection terminal connected to the semiconductor substrate with an ohmic contact; and a second electrode deposited on a bottom side of the semiconductor substrate, wherein a resistor is provided between the first electrode and the second electrode.

Abstract: A fan-out wafer-level packaging method and the package produced thereof are provided in the present application.

Abstract: A sensor wafer may be configured for in-situ measurements of parameters during an etch process. The sensor wafer may include a substrate, a cover, and one or more components positioned between the substrate and the cover. An etch-resistant coating is formed on one or more surfaces of the cover and/or substrate. The coating is configured to resist etch processes that etch the cover and/or substrate for a longer period than standard thin film materials of the same or greater thickness than the protective coating.