Patents Examined by Fernando Hidalgo
  • Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations
    Patent number: 10600478
    Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 24, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Michail Tzoufras, Marcin Gajek, Kadriye Deniz Bozdag
  • Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations
    Patent number: 10593396
    Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 17, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Michail Tzoufras, Marcin Gajek
  • Double data rate (DDR) memory controller apparatus and method
    Patent number: 10586585
    Abstract: In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 10, 2020
    Assignee: UNIQUIFY IP COMPANY, LLC
    Inventors: Mahesh Gopalan, David Wu, Venkat Iyer
  • Simultaneous scan chain initialization with disparate latches
    Patent number: 10586606
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same
    Patent number: 10586586
    Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes isolation transistors, equalization transistors and precharge transistors that are used to provide threshold voltage compensation.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kyuseok Lee, Sangmin Hwang, Si-Woo Lee
  • Storage element and storage apparatus
    Patent number: 10580471
    Abstract: A storage element includes a layer structure including a storage layer having a direction of magnetization which changes according to information, a magnetization fixed layer having a fixed direction of magnetization, and an intermediate layer disposed therebetween, which intermediate layer contains a nonmagnetic material. The magnetization fixed layer has at least two ferromagnetic layers having a direction of magnetization tilted from a direction perpendicular to a film surface, which are laminated and magnetically coupled interposing a coupling layer therebetween. This configuration may effectively prevent divergence of magnetization reversal time due to directions of magnetization of the storage layer and the magnetization fixed layer being substantially parallel or antiparallel, reduce write errors, and enable writing operation in a short time.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 3, 2020
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
  • Circuit for wordline autobooting in memory and method therefor
    Patent number: 10573365
    Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving a global word line to a first voltage. Driving the global word line to a first voltage results in a second voltage passed to the word lines. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 25, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam
  • Systems and methods for controlling data strobe signals during read operations
    Patent number: 10573371
    Abstract: An apparatus may include a first data strobe (DQS) output buffer (OB), a second DQS OB and control logic. The first data strobe (DQS) output buffer (OB) and the second DQS OB are each coupled to a DQS terminal. The first DQS OB and the second DQS OB are configured to provide a DQS signal to the DQS terminal responsive to a read clock signal. The control logic is configured to receive the read clock signal to control the first DQS OB and the second DQS OB. The apparatus is configured to selectively prevent the control logic from receiving the read clock signal while the DQS signal is being provided to the DQS terminal.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tsugio Takahashi
  • Nonvolatile memory device, semiconductor device, and electronic apparatus
    Patent number: 10566064
    Abstract: A nonvolatile memory device includes: a plurality of first reference cells that are connected in parallel, and are in an intermediate state between an erased state and a programmed state; a first current mirror circuit that generates a first mirror current proportional to a sum of currents flowing through the plurality of first reference cells in a state in which the plurality of first reference cells are selected; and a sense amplifier that, in a readout mode, generates a reference current based on at least the first mirror current, and reads out data stored in a memory cell by comparing a current flowing through the memory cell with the reference current.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: February 18, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Takeshi Miyazaki
  • Processing object data
    Patent number: 10558200
    Abstract: In one example, an additive manufacturing system includes a processing system to obtain characteristic data including conditions under which a heat reservoir may be added close to a portion of the object, based on the characteristic data, add sacrificial structure data to the three-dimensional object data for a sacrificial heat reservoir structure close to a portion of the object and not connected to the object, and generate multiple slice images from the three-dimensional object data including the sacrificial structure data.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: February 11, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Alejandro Manuel de Pena, Sebastia Cortes Herms, Josep Giralt Adroher
  • Multi-bit cell read-out techniques
    Patent number: 10559338
    Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to program the state of a corresponding one of N cell elements of the MBC to a respective state parameter value. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: February 11, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Michail Tzoufras, Marcin Gajek, Kadriye Deniz Bozdag, Mourad El Baraji
  • Memory device with a signal control mechanism
    Patent number: 10559343
    Abstract: A memory device includes an internal storage unit configured to store mode data specifying an operating speed of the memory device; a control decoder coupled to the internal storage unit, the control decoder configured to generate a delay control signal based on the mode data; and an input buffer coupled to the control decoder, the input buffer configured to adjust a delay of an input signal based on the delay control signal.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: February 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Akira Yamashita, Kenji Asaki
  • Architecture for coupling quantum bits using localized resonators
    Patent number: 10546994
    Abstract: A technique relates a superconducting microwave cavity. An array of posts has different heights in the cavity, and the array supports a localized microwave mode. The array of posts includes lower resonant frequency posts and higher resonant frequency posts. The higher resonant frequency posts are arranged around the lower resonant frequency posts. A first plate is opposite a second plate in the cavity. One end of the lower resonant frequency posts is positioned on the second plate so as to be electrically connected to the second plate. Another end of the lower resonant frequency posts in the array is open so as not to form an electrical connection to the first plate. Qubits are connected to the lower resonant frequency posts in the array of posts, such that each of the qubits is physically connected to one or two of the lower resonant frequency posts in the array of posts.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oliver Dial, Jay M. Gambetta, Douglas T. McClure, III, Matthias Steffen
  • Semiconductor memory device and control method of semiconductor memory device
    Patent number: 10546630
    Abstract: According to an embodiment, there is provided a semiconductor memory device comprising: a global bit line; a local bit line to which a plurality of cell transistors are connected; a switch connected to the local bit line; signal lines connected to the plurality of cell transistors; and a control circuit, wherein the control circuit selects a cell transistor to be selected by setting a potential of the signal line of the cell transistor to be selected to a first potential, changes a potential of the global bit line, changes a potential of the local bit line, and turns on the switch to connect the local bit line to the global bit line after changing the potential of the global bit line and the potential of the local bit line.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: January 28, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventor: Toshiaki Dozaka
  • Determining read voltages for a storage device
    Patent number: 10541034
    Abstract: Systems and methods presented herein provide for computing read voltages for a storage device. In one embodiment, a controller is controller is operable to soft read data from a portion of the storage device, and to iteratively test the soft read data a predetermined number of times. For example, the controller may test the soft read data a number of times by applying a different probability weight to the soft read data each time the soft read data is tested. The controller may then decode the soft read data based on the probability weight, and determine an error metric of the decoded soft read data. Then, the controller determines a read voltage for the portion of the storage device based on the probability weight and the error metric.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 21, 2020
    Assignee: Seagate Technology LLC
    Inventors: Nicholas Odin Lien, Ryan James Goss
  • Methods and apparatus to diagnose a valve using electric valve actuators
    Patent number: 10533682
    Abstract: Methods and apparatus to diagnose a valve using electric valve actuators are disclosed. An example apparatus includes an electric motor to actuate a valve, rotation sensors to monitor a rotation of a drive shaft associated with the electric motor to determine a distance travelled by the drive shaft, and a valve position sensor to monitor a position of a flow control member of the valve. The example electric valve actuator further includes a processor to generate an alert based on feedback from the rotation sensors and the valve position sensor, the alert associated with a failure of the valve.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: January 14, 2020
    Assignee: Fisher Controls International LLC
    Inventors: Clyde T. Eisenbeis, Thomas Pesek, Ross Schade
  • Configuring dynamic random access memory refreshes for systems having multiple ranks of memory
    Patent number: 10535393
    Abstract: An electronic device including a memory functional block having multiple ranks of memory and a memory controller functional block coupled to the memory. The memory controller includes refresh logic that detects, based on buffered memory accesses for each rank of memory of the ranks of memory, two or more ranks of memory for which a refresh is to be performed during a refresh interval. Based at least in part on one or more properties of buffered memory accesses for the two or more ranks of memory, the refresh logic determines a refresh order for performing refreshes for the two or more ranks of memory during the refresh interval. The memory controller then performs, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval.
    Type: Grant
    Filed: July 21, 2018
    Date of Patent: January 14, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Kedarnath Balakrishnan
  • Architecture for coupling quantum bits using localized resonators
    Patent number: 10529909
    Abstract: A technique relates a superconducting microwave cavity. An array of posts has different heights in the cavity, and the array supports a localized microwave mode. The array of posts includes lower resonant frequency posts and higher resonant frequency posts. The higher resonant frequency posts are arranged around the lower resonant frequency posts. A first plate is opposite a second plate in the cavity. One end of the lower resonant frequency posts is positioned on the second plate so as to be electrically connected to the second plate. Another end of the lower resonant frequency posts in the array is open so as not to form an electrical connection to the first plate. Qubits are connected to the lower resonant frequency posts in the array of posts, such that each of the qubits is physically connected to one or two of the lower resonant frequency posts in the array of posts.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oliver Dial, Jay M. Gambetta, Douglas T. McClure, III, Matthias Steffen
  • Offset memory component automatic calibration (AUTOCAL) error recovery for a memory sub-system
    Patent number: 10529433
    Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Gary F. Besinga, Michael G. Miller, Renato C. Padilla
  • Building automation system controller with real time software configuration and database backup
    Patent number: 10528015
    Abstract: A building automation system (BAS) controller configured for use in a BAS is disclosed. The BAS controller includes an internal storage device for storing a first type of data and a second type of data, and a processor in operative communication with the internal storage device. The BAS controller is configured to automatically store the first type of data and the second type of data to the internal storage device and the second type of data to an external storage device.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: January 7, 2020
    Assignee: Trane International Inc.
    Inventor: Thomas Christopher Basterash