Abstract: A semiconductor device includes a substrate including a doped region of a first doping concentration that extends downward from an upper surface of the substrate; a first stack on the upper surface, including first insulating layers and first conductive layers alternatively stacked, a first channel layer, a first memory layer and a first conductive connector configured to receive a first voltage, the first conductive connector on the first channel layer, having a second doping concentration; a second stack on the first stack including second insulating layers and second conductive layers alternatively stacked, a second channel layer, a second memory layer, the second conductive layer configured to receive the second voltage; a second conductive connector on the second channel layer, configured to receive an erasing voltage, the first conductive connector electrically connected to the first and second channel layers; the first doping concentration smaller than the second doping concentration.

Abstract: A charge sharing type lower-cell-voltage (LCV) write assist takes advantage of unused metal layers on top of a memory array to implement capacitance without incurring area costs. Only one-time fixed amount expenses of charge are needed for a given LCV level during the charge sharing phase of each write operation. Metal wires parallel to the bit cell power wires have good capacitance matching for charge sharing among all memory density configurations, thus benefitting memory compiler design.

Abstract: A memory device and an electronic device are provided. Different embodiments of local redundancy decoder circuits that can be used in the memory device and the electronic device are disclosed.

Abstract: A nonvolatile memory device includes: a plurality of word lines that are stacked; a vertical channel region suitable for forming a cell string along with the word lines; and a voltage supplier suitable for supplying a plurality of biases required for a program operation on the word lines, where a negative bias is applied to neighboring word lines disposed adjacent to a selected word line at an end of a pulsing section of a program voltage which is applied to the selected word line.

Abstract: A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.

Abstract: A semiconductor memory cell includes a memory cell, a word line and a source line both connected to the memory cell, and a control circuit. During a read operation on the memory cell, the control circuit applies a first voltage to the word line, applies a second voltage greater than the first voltage to the word line, and then applies a third voltage which is greater than the first voltage and smaller than the second voltage to the word line. During the read operation on the memory cell, the control circuit also applies a fourth voltage to the source line according to a timing at which the second voltage is applied to the word line, and then applies a fifth voltage smaller than the fourth voltage to the source line.

Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: writing a first data and a second data to a first physical erasing unit; copying the first data from the first physical erasing unit to a second physical erasing unit; and copying the second data from the first physical erasing unit to a third physical erasing unit, wherein the memory sub-module to which the second physical erasing unit belongs is different from the memory sub-module to which the third physical erasing unit belongs.

Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuitry for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

Abstract: Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.

Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

Abstract: Techniques are provided for operating non-volatile storage. Peak current consumption may be reduced in connection with sensing non-volatile memory cells. Peak current consumption may be reduced when a first read condition is present. In one aspect, the value of a parameter of a voltage that is applied to a word line during a pre-read phase of a sense operation is controlled in order to reduce peak current consumption when the first read condition is present. Examples of the parameter include a ramp rate, a number of intermediate voltage levels, and a start time.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell; a first word line coupled to the first memory cell; a first sense amplifier including a first transistor; a first bit line which couples the first memory cell to the first transistor; and a first driver configured to supply a first control signal to a gate of the first transistor. The first driver includes a first circuit configured to compare the first control signal and a second control signal to generate a third control signal based on a comparison result.

Abstract: A memory device includes memory cells operably connected to column signal lines and to word signal lines. The column signal lines associated with one or more memory cells to be accessed (e.g., read) are precharged to a first voltage level. The column signal lines not associated with the one or more memory cells to be accessed are precharged to a second voltage level, where the second voltage level is less than the first voltage level.

Abstract: A delay control circuit, which may be included in a memory device, includes a delayed signal generator configured to generate an output signal by delaying an input signal in response to a delay control signal and a delay information generator configured to generate delay information indicating an output delay between the input signal and the output signal. The delay control circuit also includes a delay control signal generator configured to, based on a result of a comparison between target delay information indicating a target delay between the input signal and the output signal and based on the delay information, generate the delay control signal for controlling the output delay and fix the output delay at the target delay in response to the delay control signal.

Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.

Abstract: A storage element includes a layer structure including a storage layer having a direction of magnetization which changes according to information, a magnetization fixed layer having a fixed direction of magnetization, and an intermediate layer disposed therebetween, which intermediate layer contains a nonmagnetic material. The magnetization fixed layer has at least two ferromagnetic layers having a direction of magnetization tilted from a direction perpendicular to a film surface, which are laminated and magnetically coupled interposing a coupling layer therebetween. This configuration may effectively prevent divergence of magnetization reversal time due to directions of magnetization of the storage layer and the magnetization fixed layer being substantially parallel or antiparallel, reduce write errors, and enable writing operation in a short time.

Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.

Abstract: Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.

Abstract: Adaptive read-threshold schemes for a memory system determine read-threshold with the lowest BER/UECC failure-rates while continuing to serve the host-reads with the required QoS. When it is determined that the QoS or other quality metric is not met for a particular read-threshold, which may be an initial, default, read-threshold, the performance of other read-thresholds are estimated. These estimates may then be used to determine an optimal read-threshold. During the iterative process, selection variables, e.g., how many times, and for which read commands, to use each of the non-default read-thresholds in future read-attempts may be determined on-the-fly.

Abstract: A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.