Patents Examined by Fernando Hidalgo
  • Patent number: 11361833
    Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Gary F. Besinga, Michael G. Miller, Renato C. Padilla
  • Patent number: 11353513
    Abstract: The invention is directed toward a primary AA alkaline battery. The primary AA alkaline battery includes an anode; a cathode; an electrolyte; and a separator between the anode and the cathode. The anode includes an electrochemically active anode material. The cathode includes an electrochemically active cathode material. The electrolyte includes potassium hydroxide. The primary AA alkaline battery has an integrated in-cell ionic resistance (Ri) at 22° C. of less than about 39 m?. The separator has a porosity of greater than 70%.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: June 7, 2022
    Assignee: DURACELL U.S. OPERATIONS, INC.
    Inventors: Michael Pozin, Brianna Rose Derooy, Nikolai N. Issaev
  • Patent number: 11348632
    Abstract: In accordance with one embodiment, a computer-implemented method is provided, comprising the act of: configuring code or hardware to cause at least part of the hardware to operate as a double data rate (DDR) memory controller and to: produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of: at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: May 31, 2022
    Assignee: UNIQUIFY, INC.
    Inventors: Mahesh Gopalan, David Wu, Venkat Iyer
  • Patent number: 11348934
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: May 31, 2022
    Assignee: Kioxia Corporation
    Inventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami
  • Patent number: 11340831
    Abstract: A memory system is provided. The memory system includes a memory controller and a data bus electrically coupled to the memory controller. The memory system further includes one or more memory devices communicatively coupled to the memory controller via the data bus, wherein each of the one or more memory devices comprises a read training setting configured to adjust a read output timing of data being sent to the memory controller during read operations from the one or more memory devices.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yang Lu, Christopher Heaton Stoddard
  • Patent number: 11340686
    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: May 24, 2022
    Assignee: Rambus Inc.
    Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
  • Patent number: 11328756
    Abstract: A semiconductor system includes a controller configured to output a clock, a command and an address; and a semiconductor device configured to generate a flag signal by detecting an input time of the command, which is input in synchronization with the clock in a write auto-precharge operation based on the command, and configured to generate an internal address for performing the write auto-precharge operation, by serializing the address and then parallelizing the flag signal and the serialized address.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Ki Hun Kwon
  • Patent number: 11327884
    Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Zhengang Chen, Jianmin Huang
  • Patent number: 11329654
    Abstract: A delay circuit of a delay-locked loop (DLL) circuit includes: a phase splitter configured to split a phase of a reference clock signal to output a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees; a logic gate configured to delay the second reference clock signal to output a delayed reference clock signal; and a delay line circuit including a plurality of delay cells that are cascade-connected, the delay line circuit configured to delay the first reference clock signal and the delayed reference clock signal based on a control code set, and to output a first delayed clock signal and a second delayed clock signal having a delay amount corresponding to a delay of one logic gate included in the plurality of delay cells.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: May 10, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hundae Choi, Garam Choi
  • Patent number: 11321009
    Abstract: A Dual In-Line Memory Module (DIMM) includes a plurality of memory devices mounted on a circuit board of the DIMM. The memory devices are arranged to be accessed via at least two memory channels. The DIMM further includes an array of surface contact connections. Each surface contact connection is configured to be engaged with an associated contact element of a z-axis compression connector. The array of surface contact connections are arranged to conduct signals for the memory channels. The memory devices are placed upon the memory circuit board in an array of X rows of memory devices and Y columns of memory devices, where X and Y are integers. When the DIMM has a first number of the memory devices A=X1×Y1 that is less than when the DIMM has a second number of memory devices B=X2×Y2, then either X1 is less than X2, or Y1 is less than Y2.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: May 3, 2022
    Assignee: Dell Products L.P.
    Inventors: Arnold Thomas Schnell, Joseph Daniel Mallory
  • Patent number: 11315619
    Abstract: Apparatuses and methods for distributing row hammer refresh events across a memory device is disclosed. In one embodiment, the present disclosure is directed to an apparatus that includes a first memory configured to receive a sequential series of refresh commands and to replace a first of the sequential refresh commands with a row hammer refresh operation once during a refresh steal cycle, a second memory configured to receive the sequential series of refresh commands at to replace a second of the sequential refresh command with a row hammer refresh operation once during a refresh steal cycle, wherein the first of the sequential refresh commands and the second of the sequential refresh commands are different commands.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Gregg D. Wolff
  • Patent number: 11314462
    Abstract: An interface circuit includes; a transmitter interface circuit including an output pad and configured to receive a first input data signal and generate a second input data signal from the first input data signal, and a receiver interface circuit including an input pad and configured to receive the second input data signal via the output pad and an internal channel The transmitter interface circuit also includes an equalization signal generation circuit configured to receive the first input data signal, generate a pulse signal by delaying the first input data signal by applying a target delay time or a target width adjustment to the first input data signal, generate an equalization signal based on the pulse signal, and provide the equalization signal to the output pad to suppress a reflected wave on the internal channel.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: April 26, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kihwan Seong, Donguk Park
  • Patent number: 11307771
    Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Suryanarayana B. Tatapudi, John David Porter, Jaeil Kim, Mijo Kim
  • Patent number: 11309029
    Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventors: Han Soo Joo, Bong Yeol Park, Ji Hyun Seo, Hee Youl Lee
  • Patent number: 11309041
    Abstract: Apparatuses and techniques are described for determining if a block of memory cells is slow-erasing during an erase operation for the block. An erase operation performs an additional verify test in a specified erase-verify iteration to check the position of the upper tail of the threshold voltage distribution of the memory cells of a block. If the upper tail is too high, this indicates a slow-erasing block, even if the erase operation is successfully completed within an allowable number of erase-verify iterations. The additional verify test can be initiated using a prefix command which is transmitted with an erase command to the memory chip. Or, it can be initiated by a device parameter on the memory chip.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: April 19, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Liang Li, Ming Wang
  • Patent number: 11288600
    Abstract: Provided are a computer program product, system, and method for determining sectors of a track to stage into cache using a machine learning module. Performance attributes of system components affected by staging tracks from the storage to the cache are provided to a machine learning module. An output is received, from the machine learning module having processed the provided performance attributes, indicating a staging strategy indicating sectors of a track to stage into the cache comprising one of a plurality of staging strategies. Sectors of an accessed track that is not in the cache are staged into the cache according to the staging strategy indicated in the output.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: March 29, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 11288188
    Abstract: Metadata is dynamically relocated in a DRAM from a virtual page that does not map to the same DRAM row in which the associated data is located, to that same DRAM row. If the target of a data access request is a location in a first page that is configured to store metadata rather than data, then a second location in a second page may be determined, and the requested data may be accessed at the second location. The associated metadata may be accessed at the location in the first page, which is configured in the virtual domain to store data but is configured in the physical domain to store the metadata associated with the data in the first page.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: March 29, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Gopi Tummala, Hirai Nandu, Subbarao Palacharla, Syed Minhaj Hassan, Sai Ramesh Bhyravajosula, Anurag Nannaka
  • Patent number: 11289146
    Abstract: Methods, systems, and devices for word line timing management are described. In some examples, a digit line may be precharged as part of accessing a memory cell. The memory cell may include a storage component and a selection component. A word line may be coupled with the selection component, and the word line may be selected in order to couple the storage component with the digit line, by way of the selection component. The word line may be selected while the digit line is still being precharged, and the storage component may become coupled with the digit line with reduced delay after the end of precharging of the digit line, concurrent with the end of the precharging of the digit line, or while the digit line is still being charged. Related techniques for sensing a logic state stored by the memory cell are also described.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Di Vincenzo, Ferdinando Bedeschi, Riccardo Muzzetto
  • Patent number: 11282567
    Abstract: Systems and methods for read operations and management are disclosed. More specifically, this disclosure is directed to receiving a first read command directed to a first logical address and receiving, after the first read command, a second read command directed to a second logic address. The method also includes receiving, after the second read command, a third read command directed to a third logical address and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command sequentially.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Tomoko Ogura Iwasaki, Tracy D. Evans, Avani F. Trivedi, Aparna U. Limaye, Jianmin Huang
  • Patent number: 11281392
    Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a criticality value can be determined and used as a basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a criticality value associated with performing a garbage collection operation satisfies a condition. Based on determining that the condition is satisfied, a parameter associated with performing the garbage collection operation can be adjusted. The garbage collection operation is performed on the data block stored on the memory component using the adjusted parameter.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jianmin Huang, Aparna U. Limaye, Avani F. Trivedi, Tomoko Ogura Iwasaki, Tracy D. Evans