Abstract: First and second data output circuits obtain corresponding parts of read data of a storage circuit to output to first and second input/output pads in a second test mode. First and second data input circuits obtain output data of the first and second data output circuits via the first and second input/output pads to output in the second test mode. A comparison object selection circuit selects output data of the first and second data input circuits to output in the second test mode. A judging circuit performs a test judgment by comparing output data of the comparison object selection circuit with expected value data and outputs a test result signal in the second test mode.

Abstract: A system and method are disclosed for providing an electrically programmable read only memory (EPROM) in which each memory cell comprises an NMOS select transistor with a thick gate oxide and a PMOS breakdown transistor with a thin gate oxide. The source of the NMOS transistor and the source, drain and N well of the PMOS transistor are connected. The gate of the PMOS transistor is grounded. Under the control of the NMOS transistor, a programming voltage pulse is passed to the N well of the PMOS transistor of a selected memory cell. The magnitude of the voltage is sufficient to break the thin gate oxide of the PMOS transistor without damaging the NMOS transistor. Because the memory state of the memory cell depends on the breakdown status of the PMOS transistor, the data may be retained in the memory cell for an unlimited period of time.

Abstract: A multi-bit memory cell stores information corresponding to a high resistive state and multiple other resistive states lower than the high resistive state. A resistance of a memory element within the multi-bit memory cell switches from the high resistive state to one of the other multiple resistive states by applying a corresponding current to the memory element.

Abstract: An inadvertent write can be prevented when a read is performed. The duration of the write current pulse for writing information in the magnetic memory layer is longer than the duration of the read current pulse for reading the information from the magnetic memory layer.

Abstract: A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.

Abstract: A semiconductor device having a register and an information generation circuit can reduce data to be transferred, and consequently save electric power. The register stores first information. The information generation circuit generates, in response to a signal acquired from the an exterior of the device, second information indicating which bits of the first information is to be inverted.

Abstract: Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system comprises a first layer of microscale signal lines, a second layer of microscale signal lines, a first layer of nanowires configured so that each first layer nanowire overlaps each first layer microscale signal line, and a second layer of nanowires configured so that each second layer nanowire overlaps each second layer microscale signal line and overlaps each first layer nanowire. The crossbar-memory system includes nonlinear-tunneling resistors configured to selectively connect first layer nanowires to first layer microscale signal lines and to selectively connect second layer nanowires to second layer microscale signal lines.

Abstract: A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate as underlying the cell array for data reading and writing, wherein the variable resistance element comprises a recording layer composed of a composite compound containing at least two types of cation elements, at least one type of the cation element being a transition element having “d” orbit, in which electrons are incompletely filled, the shortest distance between adjacent cation elements being 0.32 nm or less.

Abstract: Disclosed is a FIFO peek access device that utilizes a peek signal to access data stored in a FIFO without losing or erasing data. The peek signal is applied to read address logic and prevents the incrementing of the pointers in the peek address logic, so that after a read enable signal is asserted, the same data block can be accessed again on the next read enable signal.

Abstract: Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.

Abstract: One time programmable memory devices are disclosed that are programmed using hot carrier induced degradation to alter one or more transistors characteristics. A one time programmable memory device is comprised of an array of transistors. Transistors in the array are selectively programmed using hot carrier induced changes in one or more transistor characteristics, such as changes to the saturation current, threshold voltage or both, of the transistors. The changes to the transistor characteristics are achieved in a similar manner to known hot carrier transistor aging principles. The disclosed one time programmable memory devices are small and programmable at low voltages and small current.

Abstract: A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target threshold levels.

Abstract: An address replacing circuit includes a sub-bank region selecting unit that allows a first sub-bank region or a second sub-bank region to be selectively activated, in response to a row address and first and second bits of a column address in accordance with operation modes a first column region activating unit that generates a first column region activating address and a second column region activating address from the first bit of the column address, a second column region activating unit that generates a third column region activating address and a fourth column region activating address from the second bit of the column address, and a column region selecting unit that allows at least one of first to fourth column regions of the first sub-bank region and first to fourth column regions of the second sub-bank region to be selectively activated, in response to the first to fourth column region activating addresses.

Abstract: A semiconductor memory device including: a package; a first semiconductor chip provided in the package; a first nonvolatile memory provided on the first semiconductor chip; a second semiconductor chip provided in the package; a second nonvolatile memory provided on the second semiconductor chip; a system bus provided in the package, the system bus connecting the first and second nonvolatile memories; a plurality of data terminals exposed to outside of the package, the data terminals being connected to the first and second nonvolatile memories through the system bus; and an enable terminal exposed to the outside of the package, the enable terminal being connected to the first and second nonvolatile memories.

Abstract: A system includes a plurality of memory devices connected in-series that communicate with a memory controller. When a memory device receives a command strobe signal indicating the start of a command having an ID number, the memory device is placed in a de-selected state and the ID number is compared to the memory device's device address. Delayed versions of the command strobe signal and the command are forwarded while the memory device is in the de-selected state. If the ID number matches the device address with reference to the ID number, the memory device is placed in a selected state. In the selected state, the memory device may refrain from forwarding the delayed versions of the command strobe signal and the command, such that if there is a match, a truncated part of the command is forwarded before the memory device is placed in the selected state.

Abstract: Embodiments of the invention relate generally to a coupling device, to a processor arrangement, to a data processing arrangement, and to methods for transmitting data. In an embodiment of the invention, a coupling device for coupling a memory, which has a serial data output, with a processor, which has a parallel data input, is provided. The coupling device may include a serial data interface configured to receive data, a parallel data interface configured to transmit data, and a cache memory coupled to the serial data interface and to the parallel data interface, wherein the cache memory is configured to receive and store data, which have been received in a serial data format via the serial data interface, and to transmit data stored in the cache memory to the parallel data interface.

Abstract: A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

Abstract: A memory capable of suppressing increase of the chip area thereof while increasing a read voltage is obtained. This memory comprises a memory cell array including a plurality of subarrays, a sub bit line arranged on each subarray and provided to be connectable to a main bit line, a storage portion connected between the word line and the sub bit line and a first transistor having a gate connected to the sub bit line and a first source/drain region connected to the main bit line for controlling the potential of the main bit line on the basis of the potential of the sub bit line in a read operation.

Abstract: A memory cell array includes a plurality of non-volatile semiconductor memory elements, each memory element storing data in a non-volatile manner. A shift register stores data read from the semiconductor memory element and sequentially transfers the data outside, the shift register also stores data transferred from outside and stores the data in the semiconductor memory element. A syndrome generation circuit is connected to an output terminal of the shift register, the syndrome generation circuit generating syndrome of data output from the output terminal. An error-correction circuit uses the data and the syndrome to correct an error of the data.