Abstract: A method for fabricating a micromachined device with a fast release step is provided. A first undoped sacrificial layer is deposited on a structural layer. A doped sacrificial layer is deposited on the first undoped sacrificial layer. A second undoped sacrificial layer is deposited on the doped sacrificial layer to produce a layered structure. An etchant is then applied to the layered structure.

Abstract: Disclosed is a wafer-level package.

Abstract: A radiation emitting device of the present invention includes at least one radiation emitter, first and second electrical leads electrically coupled to the radiation emitter, and an integral encapsulant configured to encapsulate the radiation emitter and a portion of the first and second electrical leads. The encapsulant has at least a first zone and a second zone, where the second zone exhibits at least one different characteristic from the first zone. Such different characteristics may be a physical, structural, and/or compositional characteristic. Preferably, the at least one different characteristic includes at least one of the following: mechanical strength, thermal conductivity, thermal capacity, coefficient of thermal expansion, specific heat, oxygen and moisture impermeability, adhesion, and transmittance with respect to radiation emitted from the radiation emitter. The radiation emitter may be in a form of an emitter, and is preferably an LED.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

Abstract: A charge transfer device is provided which is capable of reducing a reset field-through noise in a stable manner without being affected by characteristics of transistors and without occurrence of a mustache-shaped pulse-like noise. The charge transfer device is made up of a floating diffusion region used to convert a signal charge transferred from a CCD (Charge Coupled Device) into a voltage, resetting unit used to eject the signal charge accumulated in the floating diffusion region in response to a reset pulse, a first stage source follower used to current-amplify the voltage and second stage source follower in which load is changed in response to the reset pulse and which is used to current-amplify an output voltage of the first stage source follower.

Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 &mgr;m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.

Abstract: Increased pixel density and increased sensitivity to blue light are provided in a charge couple device employing sidewall and surface gates.

Abstract: A redundant circuit of the semiconductor memory device is composed of a fuse block which assigns addresses of defective memory cells by selectively disconnecting fuses of the fuse block, address latches which individually generate and hold fuse information depending on whether the fuses are supplied with currents or not at the time of initialization, a redundant circuit-selecting latch which generates and holds fuse information depending on whether a redundant circuit-selecting fuse is supplied with a current or not and outputs a terminal voltage of the redundant circuit-selecting fuse at the time of initialization, and a N-type MOS transistor which forms returning paths of the currents flowing through the fuses of the fuse block in accordance with the terminal voltage of the redundant circuit-selecting fuse.

Abstract: A field emission display has electron emitters that are current-limited by implanting in a silicon layer only enough ions to produce a desired current, and then forming emitters from the silicon layer by isotropic etching.

Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.

Abstract: A gate insulating film 103 is oxidized by a thermal oxidation method using a gate electrode 104 as a mask. At this time, the thickness of the gate insulating film 103 becomes thicker so that the portions indicated by 106 and 107 are obtained. The thickness of an active layer becomes thin at an end 112 of a channel, so that the distance from the gate electrode becomes long by the thickness. Then the strength of an electric field between a source and drain is relaxed by this portion. In this way, a thin film transistor having improved withstand voltage characteristics and leak current characteristics is obtained.

Abstract: A fuse array having a plurality of fusible links that can be addressed by two electrodes is disclosed. The fuse array includes two conductive strips having the plurality of fusible links located therebetween and electrically coupled to the conductive strips. The fusible links have different electrical resistance and each fusible link includes a fuse portion. A voltage potential applied across the conductive strips induces current flow through the fusible links in accordance with Ohm's law and ohmic heating occurs at the fuse portion in proportion to the square of the current. The voltage is increased to cause sufficient ohmic heating to occur in the most conductive fusible link (the fusible link having the lowest electrical resistance) so that the fuse portion in that fusible link fuses.

Abstract: On a glass sheet, undercoating layers and a transparent conductive film containing tin oxide as the main component are formed in this order. The surface of the transparent conductive film is provided with roughness including convex portions and concave portions. The convex portions have a mean diameter in a range between 0.05 &mgr;m and 0.3 &mgr;m and include five convex portions or less with diameters of at least 0.5 &mgr;m per 100 &mgr;m2 of the surface. On the transparent conductive film, a photovoltaic unit and a back electrode are formed, thus obtaining a photoelectric conversion device.

Abstract: A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conducti

Abstract: The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect, is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted.

Abstract: To fabricate a crystalline semiconductor film with controlled locations and sizes of the crystal grains, and to utilize the crystalline semiconductor film in the channel-forming region of a TFT in order to realize a high-speed operable TFT. A translucent insulating thermal conductive layer 2 is provided in close contact with the main surface of a substrate 1, and an insular or striped first insulating layer 3 is formed in selected regions on the thermal conductive layer. A second insulating layer 4 and semiconductor film 5 are laminated thereover. The semiconductor film 5 is first formed with an amorphous semiconductor film, and then crystallized by laser annealing. The first insulating layer 3 has the function of controlling the rate of heat flow to the thermal conductive layer 2, and the temperature distribution difference on the substrate 1 is utilized to form a single-crystal semiconductor film on the first insulating layer 3.

Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

Abstract: A semiconductor-supporting device comprising a substrate made of an insulating material, a conductive member buried in the substrate, and a terminal connected to the conductive member and made of an electrically conductive metallic matrix-ceramic composite body.

Abstract: A thin-film semiconductor device comprising at least a semiconductor element and a wiring is disclosed. A thin film of a protective insulating material is formed on the lower surface of the semiconductor element, and a substrate is bonded on the lower surface of the thin film. A method for fabricating the thin-film semi-conductor device is also disclosed, in which a thin-film semiconductor circuit is formed on a silicon-on-insulator wafer, the silicon substrate on the reverse side of the silicon-on-insulator wafer is etched off, a thin-film semiconductor chip is formed and attached to the of substrate, and the thin-film semiconductor chip and the substrate are wired to each other by printing.