Abstract: A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line.

Abstract: A semiconductor device has a dummy pattern including an underlying layer which is formed on a semiconductor substrate and in which a plurality of word lines from N−2 to N+2 are arranged in parallel, a plurality of blocks each of which has a plurality of dummy sheets arranged in such a way that each of them spreads over the two word lines neighboring in the direction along the word lines from N−2 to N+2, and a plurality of dummy sheets arranged between the plurality of blocks in such a way that each of them spreads over the two word lines neighboring between the blocks.

Abstract: A semiconductor component includes a first connection zone of a first conductivity type for providing a contact at a first side of a semiconductor body and a second connection zone of the first conductivity type for providing a contact at the second side of the semiconductor body. A drift zone adjoins the first connection zone and extends in a vertical direction of the semiconductor body as far as the second side of the semiconductor body. A body zone of a second conductivity type is disposed between the second connection zone and the first connection zone or the drift zone. A control electrode is insulated from the semiconductor body and disposed above the body zone such that the control electrode substantially does not overlap with the drift zone and the second connection zone in a lateral direction. A method for manufacturing a semiconductor component is also provided.

Abstract: An optic semiconductor package includes a plate shaped substrate having an insulation layer through which two spaced apart layer apertures are formed. The substrate further includes a plurality of electrically conductive patterns formed on the wall surfaces of the layer apertures and a lower surface of the insulation layer. One of a laser diode and a photo detector are disposed in a different one of the two layer apertures and are each electrically connected to the electrically conductive patterns through conductive bumps formed on the laser diode and the photo detector. An insulation plate, having a plurality of plate apertures formed through portions of the insulation plate adjacent to the electrically conductive patterns, is coupled to the lower surface of the substrate. One of a plurality of conductive pins electrically connected with the electrically conductive patterns is fitted in each of the plate apertures of the insulation plate and extends downward from the insulation plate.

Abstract: The present invention generally relates to a method of determining a source/drain junction overlap and a channel length of a small device, such as a MOS transistor. A large reference device having a known channel length is provided, and a source, drain, and substrate on which the device has been formed are grounded. A predetermined gate voltage is applied to a gate of the large device, and a gate to channel current of the reference device is measured. A source, drain, and substrate on which the small device has been formed are grounded, and the predetermined voltage is applied to a gate of the small device, and a gate to channel current of the small device is measured. The substrate and one of the source or the drain of the small device is floated, and a predetermined drain voltage is applied to source or the drain which is not floating. A gate to drain current for the small device is measured, and a source/drain junction overlap length is calculated.

Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD.

Abstract: A functional block for a CMOS circuit within the core of an integrated circuit chip and a method of making the same is disclosed. The functional block uses both thick and thin gate oxide transistors which reduces the leakage current and increases the voltage swing while permitting the device scaling in circuits made in CMOS technology. Within the functional block, the distance between a thick oxide transistor and a thin oxide transistor is chosen based on a transistor stability criterion. The thick and thin oxide transistors can be connected to identical or different voltage sources. Further, a transistor within a functional block can be chosen to be thick or thin oxide transistor based on a leakage current threshold or a voltage swing threshold.

Abstract: A field effect transistor used in radio frequency switching applications and having a linear performance characteristic is disclosed. The transistor comprises a plurality of gate lines, a source terminal, a drain terminal, and two feed forward capacitors electrically coupled to the source and drain terminals and the gate line at a plurality of points along the line. An improved transistor preferably includes three or more gate lines to help improve harmonic suppression.

Abstract: A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions. In a further aspect of the invention, a process for forming an isolated junction in a bulk semiconductor includes forming a dielectric volume adjacent and subjacent to portions of the source and drain regions.

Abstract: The invention relates to a CCD of the buried-channel type comprising a charge-transport channel in the form of a zone (12) of the first conductivity type, for example the n-type, in a well (13) of the opposite conductivity type, in the example the p-type. In order to obtain a drift field in the channel below one or more gates (9, 10a) to improve the charge transfer, the well is provided with a doping profile, so that the average concentration decreases in the direction of charge transport. Such a profile can be formed by covering the area of the well during the well implantation with a mask, thereby causing fewer ions to be implanted below the gates (9, 10a) than below other parts of the channel. By virtue of the invention, it is possible to produce a gate (10a) combining a comparatively large length, for example in the output stage in front of the output gate (9) to obtain sufficient storage capacity, with a high transport rate.

Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.

Abstract: A semiconductor strain gage having an electrically resistive substrate layer and a layer of electrically conductive silicon supported by the substrate layer. The silicon layer can be an epitaxial silicon layer grown on a surface of the substrate layer or a diffused or ion-implanted layer formed in the surface of the substrate layer. Also, a force measuring and detecting device including a force responsive member and the above-described semiconductor strain gage attached to the force responsive member, the strain gage measuring forces applied to the force responsive member.

Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Abstract: An integrated NMOS circuit including an active stack having a plurality of isolated p-well active devices M1-M3, a bias stack having a plurality of diode-connected isolated p-well bias devices M4-M6, the gate of each of the plurality of diode-connected isolated p-well bias devices coupled to the gate of a corresponding one of the plurality of isolated p-well active devices, the bulk of each of the plurality of diode-connected isolated p-well bias devices coupled directly to the bulk of the corresponding one of the plurality of isolated p-well active devices, and the source of each of the plurality of diode-connected isolated p-well bias devices coupled directly to the bulk of the corresponding diode-connected isolated p-well bias device.

Abstract: A method for increasing the critical temperature, Tc, of a high critical temperature superconducting (HTS) film (104) grown on a substrate (102) and a superconducting structure (100) made using the method. The HTS film has an a-b plane parallel to the surface of the substrate and a c-direction normal to the surface of the substrate. Generally, the method includes providing the substrate, growing the HTS film on the substrate and, after the HTS film has been grown, inducing into the HTS film a residual compressive strain the a-b plane and a residual tensile strain into the c-direction.

Abstract: The invention reduces capacitor coupling between data read bit lines and data write bit lines to thereby prevent error detection of data. A first pair of bit lines BM and {overscore (BM)} that read data from a specified one of memory cells in a memory cell column and a second pair of bit lines BS and {overscore (BS)} that write data in another specified one of the memory cells in the memory cell column are formed in different layers through an interlayer dielectric film. As viewed in a plan view, the space between the first pair of bit lines BM and {overscore (BM)} is wider than the second pair of bit lines BS and {overscore (BS)}, and the second pair of bit lines BS and {overscore (BS)} are disposed between the first pair of bit lines BM and {overscore (BM)}. A first wiring layer that is set a ground potential is disposed in the same layer as the first pair of bit lines BM and {overscore (BM)} and between the first pair of bit lines BM and {overscore (BM)}.

Abstract: A semiconductor-on-insulator (SOI) device includes a buried insulator layer and an overlying semiconductor layer. Portions of the insulator layer are doped with the same dopant material, for example boron, as is in corresponding portions of the overlying surface semiconductor layer. A peak concentration of the dopant material may be located in the insulator material, or may be located in a lower portion of the surface semiconductor layer. The dopant material in the insulator layer may prevent depletion of dopant material from portions of the surface semiconductor layer, such as from channel portions of NMOS transistors.

Abstract: A semiconductor integrated circuit having gate array area and IP (Intellectual Property) portion. A semiconductor integrated circuit has a lower wiring region and an upper wring region on a semiconductor substrate. A gate array region is on the semiconductor substrate. An IP (Intellectual Property) region comprises a plurality of semiconductor devices formed on the semiconductor substrate and has a predetermined function. A first wiring layer is in the lower layer wiring region above the semiconductor substrate and a second wiring layer is above the IP region. A third wiring layer is in the upper wiring region of the gate array region. The third wiring layer is wider than the first and second wiring layers.

Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.

Abstract: An object of the present invention is to realize a semiconductor device having a high TFT characteristic. In manufacturing an active matrix display device, electric resistivity of the electrode material is kept low by preventing penetration of oxygen ion into the electrode in doping of an impurity ion. A display device having a low electric resistivity can be obtained.