Abstract: A new capacitor structure of a Flash memory (Flash) cells on a supporting substrate's existing topography, including existing topography provided by adjacent word lines is provided. The gate of the Flash memory cell is constructed as an integral part of the new capacitor cell structure. An increased capacitive coupling ratio is achieved whereby reduced programming voltage is required while yielding more a more compact memory cell structure. Hence, the requirements of low power densely packed integrated circuits is realized for smaller, portable microprocessor devices.

Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Abstract: A crystalline semiconductor having an even surface and a large crystal grain size is formed on an economical glass substrate using a laser crystallizing technology. A series of processes, including forming an insulation film on a glass substrate; forming a semiconductor film in the first layer; crystallizing the semiconductor film in the first layer by irradiating laser light stepwise from weak energy laser light to strong energy laser light; forming a semiconductor film in a second layer having a film thickness thinner than that of the semiconductor film in the first layer; performing laser crystallization of the semiconductor thin film in the second layer by irradiating laser light stepwise from weak energy laser light to strong energy laser light, are continuously performed without exposing the workpiece to the atmosphere.

Abstract: P-type ion implantation is done in N well 15, so as to form a charge drain control layer 17 and form a photodiode N well 16 and OFD drain 5, the result being that, even if there is variation in the potential of the photodiode N well 16 making up the photodiode, because the variation in the potential of the charge drain control layer 17 is in the same direction as the potential of the photodiode N well 16, so that variation does not occur in the maximum amount of electrical charge that can be accumulated, the result being that there is no variation in the signal in the saturation condition.

Abstract: A semiconductor device has a PN junction between first and second regions of the device in which in the intended operation of the device reverse breakdown of the junction occurs. The first region is of lower impurity concentration than the second region and a first buried region of the same conductivity type as and of higher impurity concentration than the first region is provided in the first region adjacent to the junction. A second buried region of the same conductivity type as and of higher impurity concentration than the first buried region is provided in the first buried region and one of the first and second buried regions is formed with a plurality of separate regions of small area arranged so that reverse breakdown of the junction preferentially occurs through the second buried region.

Abstract: In forming a pair of impurity regions in an active layer, an intrinsic or substantially intrinsic region having a double-sided comb shape is also formed by using a proper mask. The intrinsic or substantially intrinsic region is composed of a portion that effectively functions as a channel forming region and portions in which a channel is not formed and which function as heat sinks. The heat dissipation effect is improved because the heat sinks are formed by the same material as the channel forming region.

Abstract: A compensation circuit and method for compensating for the threshold shift in an irradiated MOSFET. The method determines the gate threshold voltage to body voltage relationship to vary the body voltage with radiation. The compensation circuit (10) has at least one MOSFET (Q2) having the same channel type as the MOSFET being compensated (Q1). The at least one matching MOSFET (Q2) is connected to the gate of the MOSFET (Q1) being compensated. At least one MOSFET (Q3, Q4) having a channel type that is different from the channel type of the MOSFET (Q1) being compensated is connected to the gate of the matching MOSFET (Q2). The result is that the compensation circuit (10) controls a negative shift in the body voltage of the MOSFET (Q1) being compensated resulting in a higher threshold voltage.

Abstract: A method is provided for packaging an integrated circuit chip that has a front face with sensors located in a central region and electrical connection areas located in a region that lies between at least one edge of the chip and the central region. According to the method, a rear face of the chip is cemented to a front face of a substrate that includes through-holes, with the rear face of the substrate including electrical connection areas that pass in front of the through-holes such that the through-holes are located laterally with respect to the edge of the chip. The electrical connection areas on the front face of the chip are connected to the electrical connection areas on the substrate through the through-holes, and the chip is embedded in an optically transparent encapsulating material so as to form an encapsulating block on the same side as the front face of the substrate. The substrate is cut around the encapsulating block, following the perimeter of the encapsulating block.

Abstract: In a semiconductor device having a plurality of thin film transistors and matrix wiring lines formed on a substrate, the matrix wiring lines are electrically connected via resistors in order to prevent electrostatic destructions during a panel manufacture process and improve a manufacture yield.

Abstract: A timing signal generating device to drive a solid-state image pickup device including a large number of photoelectric converter elements arranged in a matrix shape, a vertical transfer path arranged for each photoelectric converter element column in the vicinity thereof, and a horizontal transfer path connected to an end section of each vertical transfer path includes at least one rewritable storage in which stored information can be rewritten by an external controller and a timing signal generating section which can generate a sequence of a plurality of kinds of timing signals corresponding to an operation mode of the solid-state image pickup device according to data stored in the storage. Therefore, generating points of time, signal waveforms, and the like of various kinds of timing signals to drive a solid-state image pickup device can be easily changed according to specifications of devices using the solid-state image pickup device as an area image sensor.

Abstract: A method for fabricating a thin film transistor that has a multi-layered gate structure of large thickness and the transistors formed are disclosed. In the method, an organic polymeric material layer is spin-coated to planarize a metal gate that has a second metal material deposited in a thin layer on the gate. A suitable metal coating material is molybdenum. A novel planarization process by dry etching is then carried out utilizing a UV spectrum of Mo in an end point detection method to remove all the organic polymeric material from a top planar surface of the metal gate (and the metal coating layer) and then stopping the dry etching process. A dielectric material layer such as silicon nitride is then deposited on top of the metal gate and the remaining organic polymeric material layer to complete the isolation process for the gate.

Abstract: An image input device or a solid-state image sensing device using a CCD linear sensor includes a main sensor array and a sub sensor array. A transfer register for the sub sensor array is provided with charge sweep means for sweeping away unnecessary charges. Thus, only signals in the main sensor array are selectively read out without being affected by signals in the sub sensor array.

Abstract: A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage-activated transistors which have the same channel conduction type and are electrically connected in series between a power supply terminal and an output terminal. A source region and a body region of at least the voltage-activated transistor connected to the output terminal are electrically connected and have substantially the same potential. The semiconductor integrated circuit has either an SOI or SOS structure.

Abstract: A data input/output line structure having reduced resistance for a semiconductor memory device includes a first signal line formed from a first metal layer, the first signal line being connected to a bit line of a memory cell; a second signal line formed from a second metal layer, the second signal line being arranged parallel to the first signal line; and a plurality of strapping connectors for connecting the first signal line and the second signal line. The first and the second signal lines having first and second resistances, respectively, wherein the second resistance is lower than the first resistance.

Abstract: An embodiment of the instant invention is a memory device comprising: a memory cell including: a first transistor (108 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the first transistor; and a second transistor (130 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the second transistor and the current path of the first transistor, the current path of the second transistor connected to the backgate/body connection of the first transistor; an input/output conductor; and a pass transistor coupling the memory cell to the input/output conductor.

Abstract: A semiconductor device 100 has a peripheral cell region 102 and an internal cell region. The peripheral cell region is provided with a signal input terminal 110 that inputs input signals having different voltage levels in a normal operation mode and in a test mode starting time; a first transmission circuit 120 that provides the input signal to the internal cell region; and a second transmission circuit 150 that outputs a control signal indicating a test mode when the input signal has a voltage level equivalent to a voltage to be provided when the test mode is started. Also, a control circuit 180 that cuts off current that flows in the second transmission circuit 150 when the input signal has a voltage level to be provided in the normal operation mode. The control circuit 180 includes first and second P-type transistors 182 and 184 formed in a floating N-type well.

Abstract: A liquid crystal device, which is an example of an electro-optical device, includes a TFT, a data line, a scanning line, a second capacitor electrode, and a pixel electrode, all formed on a TFT array substrate. The pixel electrode and the TFT are electrically connected to each other via a conductive layer and via two contact holes. A second storage capacitor is formed between the second capacitor electrode and a part of the conductive layer, wherein a part of a second insulating thin film is disposed between the second capacitor electrode and the part of the conductive layer. The second insulating thin film is formed of an oxide film obtained by oxidizing the scanning line and the second capacitor electrode.

Abstract: A thin film transistor optical detecting sensor includes an array substrate having a transparent substrate, a plurality of sensor thin film transistors disposed on the transparent substrate, each having a first silicon layer of a first thickness, a plurality of storage capacitors, each connected with a corresponding one of the plurality of sensor thin film transistors, storing charges of an optical current, and a plurality of switch thin film transistors, each having a second silicon layer of a second thickness less than the first thickness.

Abstract: There is provided a combination of doping process and use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.

Abstract: An electrostatic discharge (ESD) protection circuit for protecting an internal device from an ESD is disclosed. The ESD protection circuit includes an NMOS transistor connected to a ground voltage terminal having silicide layers on a gate electrode and on source/drain regions thereof; and a PMOS transistor having a gate electrode connected to a ground voltage terminal and connecting the NMOS transistor to a pad.