Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Abstract: An electronic circuit including a semiconducting or conducting substrate having first and second opposite surfaces and at least first and second non-parallel electrically insulating trenches that extend from the first surface in the substrate, define at least one portion of the substrate and join at a junction, the portion of the substrate including a protrusion that extends to the junction.

Abstract: Electronic devices involving contact structures, and related components, systems and methods associated therewith are described. The contact structures are particularly suitable for use in a variety of light-emitting devices, including LEDs.

Abstract: A packaging method of a display panel, a display panel and a display device are provided. The packaging method includes: providing a first substrate; providing an adhesive with a magnetic material distributed therein; applying the adhesive to a surface of the first substrate to form a first adhesive layer having a first pattern; providing a magnetic field to drive the magnetic material to mobilize the adhesive on the surface of the first substrate, so as to transform the first adhesive layer having the first pattern into a second adhesive layer having a second pattern, wherein, an orthogonal projection of the first adhesive layer having the first pattern on the first substrate is different from an orthogonal projection of the second adhesive layer having the second pattern on the first substrate; and bonding a second substrate onto the adhesive layer having the second pattern.

Abstract: A radiation detector has a photoelectric conversion element array having a light receiving unit and a plurality of bonding pads; a scintillator layer stacked on the photoelectric conversion element array; a resin frame formed on the photoelectric conversion element array so as to pass between the scintillator layer and the bonding pads away from the scintillator layer and the bonding pads and so as to surround the scintillator layer; and a protection film covering the scintillator layer and having an outer edge located on the resin frame; a first distance between an inner edge of the resin frame and an outer edge of the scintillator layer is shorter than a second distance between an outer edge of the resin frame and an outer edge of the photoelectric conversion element array; the outer edge and a groove are processed with a laser beam.

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including a semiconductor substrate, an interlayer dielectric layer on the semiconductor substrate, multiple trenches extending through the interlayer dielectric layer to the semiconductor substrate and including a first trench of a first NMOS device and a second trench of a second NMOS device, and a dielectric layer on sidewalls and a bottom of the trenches, forming an NMOS work function adjustment layer on the dielectric layer, performing a first oxidation treatment on the NMOS work function adjustment layer in the first trench to form a first oxide layer, and a second oxidation treatment on the NMOS work function adjustment layer in the second trench to form a second oxide layer, and forming a metal electrode layer in the trenches. The first oxide layer has an oxygen content lower than that of the second oxide layer.

Abstract: An apparatus comprising: a plurality of sensors (501) arranged in an array (500), each sensor having a source electrode (504), a drain electrode (503), a gate electrode (505) and a channel, wherein the source electrode and drain electrode are elongate and the channel has a channel width defined by the longitudinal extent of the source and/or drain electrode and a channel length defined by the separation between the source and drain electrodes; a common conductive or semiconductive layer (506), which may be made of graphene, comprising the channels of the sensors (501) and arranged to extend over the plurality of sensors of the array and configured to be in electrical contact with at least the source electrode and the drain electrode of each sensor; and wherein the source electrode or drain electrode of each sensor forms a substantially continuous sensor perimeter at least along the channel width, which substantially encloses the other electrode of each sensor to inhibit the flow of charge carriers beyond the

Abstract: A display device according to the present disclosure has a resonator structure in which a light reflector and a semi-transmissive plate are disposed at a distance that differs for each luminescent color. In this resonator structure, a light-emitting function layer including a light-emitting layer, a transparent cathode electrode, and a protective film that protects the cathode electrode are laminated in order between the light reflector and the semi-transmissive plate. In addition, the semi-transmissive plate is formed on the protective film.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate, a buffer layer that includes at least one additional layer formed over the substrate, a channel layer formed over the buffer layer, a barrier layer formed over the channel layer forming a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and an ohmic contact recessed into the barrier layer. A method for fabricating the semiconductor device includes forming a semiconductor substrate that includes a mixed crystal layer, creating an isolation region that defines an active region along an upper surface of the semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and recessing an ohmic contact into the semiconductor substrate.

Abstract: Light emitting structures are described in which vertical inorganic semiconductor-based light emitting diodes (LEDs) with hexagon shaped sidewalls are mounted within corresponding circular reflective well structures. Diffuser layers may additionally laterally surround the hexagon shaped sidewalls within the circular reflective well structures.

Abstract: A radiation detector has a photoelectric conversion element array having a light receiving unit and a plurality of bonding pads; a scintillator layer stacked on the photoelectric conversion element array; a resin frame formed on the photoelectric conversion element array so as to pass between the scintillator layer and the bonding pads away from the scintillator layer and the bonding pads and so as to surround the scintillator layer; and a protection film covering the scintillator layer and having an outer edge located on the resin frame; a first distance between an inner edge of the resin frame and an outer edge of the scintillator layer is shorter than a second distance between an outer edge of the resin frame and an outer edge of the photoelectric conversion element array; the outer edge and a groove are processed with a laser beam.

Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.

Abstract: A vertical gate all around (VGAA) is provided. In embodiments, the VGAA has a nanowire with a first contact pad and a second contact pad. A gate electrode is utilized to help define a channel region within the nanowire. In additional embodiments multiple nanowires, multiple bottom contacts, multiple top contacts, and multiple gate contacts are utilized.

Abstract: Techniques are provided for forming a semiconductor device. In an aspect, a semiconductor device is provided that includes a silicon carbide (SiC) structure and a III-nitride structure. The SiC structure includes a drain electrode, a substrate layer that is formed on the drain electrode and includes SiC, and a drift layer formed on the substrate layer. The drift layer includes p-well regions that allow current to flow through a region between the p-well regions. The III-nitride structure includes a set of III-nitride semiconductor layers formed on the SiC structure, a passivation layer formed on the set of III-nitride semiconductor layers, a source electrode electrically coupled to the p-well regions, and gate electrodes electrically isolated from the set of III-nitride semiconductor layers. In an aspect, the SiC structure includes a transition layer that includes connecting regions. In another aspect, the III-nitride structures includes connection electrodes electrically coupled to the connecting regions.

Abstract: A magnetic element is disclosed wherein a composite seed layer such as TaN/Mg enhances perpendicular magnetic anisotropy (PMA) in an overlying magnetic layer that may be a reference layer, free layer, or dipole layer. The first seed layer is selected from one or more of Ta, Zr, Nb, TaN, ZrN, NbN, and Ru. The second seed layer is selected from one or more of Mg, Sr, Ti, Al, V, Hf, B, and Si. A growth promoting layer made of NiCr or an alloy thereof is inserted between the seed layer and magnetic layer. In some embodiments, a first composite seed layer/NiCr stack is formed below the reference layer, and a second composite seed layer/NiCr stack is formed between the free layer and a dipole layer. The magnetic element has thermal stability to at least 400° C.

Abstract: An embodiment of the present inventive concept provides an ultraviolet light emitting device comprising: a substrate having a concave or convex edge pattern disposed along an edge of an upper surface thereof; a semiconductor laminate disposed on the substrate and including first and second conductivity-type AlGaN semiconductor layers and an active layer disposed between the first and second conductivity-type AlGaN semiconductor layers and having an AlGaN semiconductor; a plurality of uneven portions extending from the edge pattern along the side surface of the semiconductor laminate in a stacking direction; and first and second electrodes connected to the first and second conductivity-type AlGaN semiconductor layers, respectively.

Abstract: Provided is an optically restorable semiconductor device including a gate electrode, a gate insulation film on the gate electrode, a photo-responsive semiconductor film on the gate insulation film, and an interface charge part disposed adjacent to an interface between the photo-responsive semiconductor film and the gate insulation film, wherein the interface charge part includes charge traps, and the interface charge part and the photo-responsive semiconductor film directly contact with each other.

Abstract: LED packages are disclosed that are compact and efficiently emit light, and can comprise encapsulants with planar surfaces that refract and/or reflect light within the package encapsulant. The LED package are also directed to features or arrangements that allow for improved or tailored emission characteristic for LED packages according to the present invention. Some of these features or arrangements include, but are not limited to, higher ratio of light source size to submount size, the used of particular materials (e.g. different silicones) for the LED package layers, improved arrangement of a reflective layer, improved composition and arrangement of the phosphor layer, tailoring the shape of the encapsulant, and/or improving the bonds between the layers. There are only some of the improvements disclosed herein, with some of these resulting in LED packages the emit light with a higher luminous intensity over conventional LED packages.