Abstract: A semiconductor device includes a semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a first insulator, a second insulator, a third insulator, and a fourth insulator. The first conductor and the semiconductor partly overlap with each other with the first insulator positioned therebetween. The second conductor and the third conductor have regions in contact with the semiconductor. The semiconductor has a region in contact with the second insulator. The fourth insulator has a first region and a second region. The first region is thicker than the second region. The first region has a region in contact with the second insulator. The second region has a region in contact with the third insulator. The fourth conductor and the second insulator partly overlap with each other with the fourth insulator positioned therebetween.

Abstract: A method for fabricating a surface emitting laser includes the steps of: preparing a processing apparatus with a first part and a second part, the processing apparatus including a first heater and a second heater that heat the first part and the second part, respectively; preparing a wafer product for forming a surface emitting laser, the wafer product including a semiconductor post including a III-V compound semiconductor layer containing aluminum as a constituent element, the III-V compound semiconductor layer being exposed at a side face of the semiconductor post; after disposing the wafer product in the second part, energizing the first heater and the second heater; supplying a first gas containing no oxidizing agent to the processing apparatus; and after stopping supplying the first gas, oxidizing the III-V compound semiconductor layer by supplying a second gas containing an oxidizing agent to the processing apparatus.

Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.

Abstract: In one embodiment, a method for fabricating a semiconductor package includes providing a multi-layer molded conductive structure. The multi-layer molded conductive structure includes a first conductive structure disposed on a surface of a carrier and a first encapsulant covering at least portions of the first conductive structure while other portions are exposed in the first encapsulant. A second conductive structure is disposed on the first encapsulant and electrically connected to the first conductive structure. A second encapsulant covers a first portion of the second conductive structure while a second portion of the second conductive structure is exposed to the outside, and a third portion of the second conductive structure is exposed in a receiving space disposed in the second encapsulant. The method includes electrically connecting a semiconductor die to the second conductive structure and in some embodiments removing the carrier.

Abstract: A semiconductor device including a semiconductor substrate including a plurality of active regions and a device isolation region for isolating the plurality of active regions; and a buried bit line and a buried gate electrode which are formed in the semiconductor substrate. The device isolation region includes a first device isolation region extending in a first direction and a second device isolation region extending in a second direction crossing with the first direction and having a shield pillar formed therein.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

Abstract: A semiconductor device includes: a sealing body that seals a first semiconductor element and a second semiconductor element; first heat-radiating members exposed at a front surface of the sealing body; second heat-radiating members exposed at a back surface of the sealing body; first signal terminals electrically connected to the first semiconductor element, and projecting from a top surface of the sealing body in a first direction; and second signal terminals electrically connected to the second semiconductor elements, and projecting from the top surface of the sealing body in the first direction. The top surface of the sealing body includes a first inclined surface, a second inclined surface, and a boundary line or a boundary range located therebetween. The boundary line or the boundary range includes at least part of a minimum creepage path between the first signal terminals and the second signal terminals.

Abstract: The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.

Abstract: Protective elements are provided for non-volatile memory cells in crossbar arrays in which each memristor is situated at a crosspoint of the array. Each memristor is provided with a protective element. The protective element includes a layer of a first oxide that upon heating converts to a second oxide having a higher resistivity than the first oxide.

Abstract: The present disclosure relates to a method for fabricating a micro-electromechanical system (MEMS) device. In the method, a carrier wafer is received. A MEMS wafer, which includes a plurality of die, is bonded to the carrier wafer. A cavity is formed to separate an upper surface of the carrier wafer from a lower surface of a die of the MEMS wafer. A separation trench is formed to laterally surround the die, wherein formation of the cavity and the separation trench leaves a tethering structure suspending the die over the upper surface of the carrier wafer. The die and carrier wafer are translated with respect to one another to break the tethering structure and separate the die from the carrier wafer.

Abstract: Fabricating a wafer-scale spacer/optics structure includes replicating optical replication elements and spacer replication sections directly onto an optics wafer (or other wafer) using a single replication tool. The replicated optical elements and spacer elements can be composed of the same or different materials.

Abstract: A method of producing a semiconductor device includes steps of: growing semiconductor layers to form a semiconductor stack on a semiconductor substrate; forming a first adhesive layer on the semiconductor stack; bonding a temporary support made of non-semiconductor material to the first adhesive layer; removing the semiconductor substrate from the semiconductor stack to expose a surface of the semiconductor stack; forming a second adhesive layer on the exposed surface of the semiconductor stack; bonding a support to the second adhesive layer; and removing the temporary support from the semiconductor stack. The support has a thermal conductivity greater than the thermal conductivities of the semiconductor layer in the semiconductor stack. In forming the first adhesive layer, this layer can cover the entire surface, or both the top and a side of the semiconductor stack. Before forming the first adhesive layer, a protective layer can be formed on the semiconductor stack.

Abstract: An electronic device includes an electronic part including a first substrate having a group of first terminals over a first front surface and having a concavity in a back surface, a filler placed in the concavity, and a flat plate placed over the back surface with the filler therebetween, and further includes a second substrate disposed on the first front surface side of the first substrate and having a group of second terminals bonded to the group of first terminals over a second front surface opposite the first front surface. The filler and flat plate minimize deformation of the first substrate and variation in the distance between the group of first terminals and the group of second terminals caused by the deformation of the first substrate, which thereby reduces the occurrence of a failure in bonding together the group of first terminals and the group of second terminals.

Abstract: An example provides a semiconductor device including an insulator with a predetermined thickness between a well region of a semiconductor substrate and a resistor of polysilicon. The insulator has a structure that is able to withstand an ultrahigh voltage, and thereby allows the manufacture of a semiconductor device resistor that can bear an ultrahigh voltage without increasing the size of a semiconductor substrate and a semiconductor device including such a resistor. Other examples provide a method for manufacturing such a semiconductor device.

Abstract: Disclosed herein, in certain embodiments, is a method of depositing a polymer onto a surface. In some embodiments, the method comprises using a high electric field and a high frequency vibratory motion to deposit a polymer solution onto the surface. Disclosed herein, in certain embodiments, is a method of manufacturing an electrode or diode. In some embodiments, the method comprises using a high electric field and a high frequency vibratory motion to deposit a polymer onto a surface. Further disclosed herein, in certain instances, is an electrode manufactured by any method disclosed herein. Further disclosed herein, in certain instances, is a diode manufactured by any method disclosed herein.

Abstract: A light emitting diode includes a first electrode, a second electrode, and an epitaxial structure. The epitaxial structure is arranged on the first electrode, and electrically connects with the first electrode and the second electrode. The second electrode surrounds periphery of the epitaxial structure to reflect light from the epitaxial structure out from the top of the epitaxial structure. A method for manufacturing the light emitting diode is also presented. The light emitting diode and the method increase lighting efficiency of the light emitting diode.

Abstract: A method for fabricating a semiconductor device may include: forming a plurality of first isolation trenches and a plurality of line-shaped active regions by etching a semiconductor substrate; forming a line-shaped device isolation region in each of the plurality of first isolation trenches; forming a plurality of second isolation trenches extending in a second direction by etching the plurality of line-shaped active regions and the plurality of line-shaped device isolation regions; forming a connection trench to connect the plurality of second isolation trenches to each other; forming a shielding line in each of the plurality of second isolation trenches; and forming a shielding line interconnection in the connection trench.

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Abstract: A semiconductor package includes a first semiconductor device provided on a support substrate; a first encapsulation material covering the first semiconductor device; a first line provided on the first encapsulation material, the first line being connected with the first semiconductor device; an intermediate buffer layer covering the first line, and a second encapsulation material provided on the intermediate buffer layer. The first encapsulation material and the second encapsulation material are each formed of an insulating material different from an insulating material used to form the intermediate buffer layer. A second semiconductor device covered with the second encapsulation material may be provided on the intermediate buffer layer.

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.