Abstract: Embodiments of the invention may include a packaged device that includes thermally stable radio frequency integrated circuits (RFICs). In one embodiment the packaged device may include an integrated circuit chip mounted to a package substrate. According to an embodiment, the package substrate may have conductive lines that communicatively couple the integrated circuit chip to one or more external components. One of the external components may be an RFIC module. The RFIC module may comprise an RFIC and an antenna. Additional embodiments may also include a packaged device that includes a plurality of cooling spots formed into the package substrate. In an embodiment the cooling spots may be formed proximate to interconnect lines the communicatively couple the integrated circuit chip to the RFIC.

Abstract: An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an upper barrier layer. The upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer. Further, the composite barrier layer comprises a gate opening. A channel layer is arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer. A gate dielectric layer is arranged over the composite barrier layer and within the gate opening. A gate electrode is arranged over the gate dielectric layer. A method for manufacturing the E-FET is also provided.

Abstract: Provided are a printed circuit board (PCB) capable of blocking introduction of impurities during a molding process so as to reduce damage on a semiconductor package, a method of manufacturing the PCB, and a method of manufacturing a semiconductor package by using the PCB. An embodiment includes an apparatus comprising: a substrate body comprising an active area and a dummy area on an outer portion of the active area, the substrate body extending lengthwise in a first direction; a plurality of semiconductor units mounted on the active area; and a barrier formed on the dummy area, wherein the barrier extends in the first direction.

Abstract: Ion sensor based on differential measurement comprising an ISFTET-REFET pair wherein the REFET is defined by a structure composed of an ISFET covered by a microreservoir where an internal reference solution is contained. The sensor comprises a first and a second ion-selective field effect transistor, an electrode, a substrate on the surface whereof are integrated the two transistors, connection tracks and the electrode and a structure adhered on the first ion-selective field effect transistor which creates a microreservoir on the gate of said first transistor, with the microreservoir having a microchannel which connects the microreservoir with the exterior and the microreservoir being filled with the reference solution.

Abstract: A light emitting device package is disclosed. The light emitting device package includes a lens, a refraction portion disposed under the lens, and a light emitting device disposed under the refraction portion, wherein the lens includes a top surface, a bottom surface opposite to the top surface, an upper recess formed in the top surface, and a lower recess formed in the bottom surface, the refraction portion is disposed at a first bottom surface of the bottom surface, the first bottom surface defining the lower recess, and the upper recess, the lower recess, the refraction portion, and the light emitting device are aligned along an optical axis.

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Abstract: A semiconductor device includes a gate structure having a gate conductor and a sidewall spacer. A partial dielectric cap is formed on the gate conductor and extends less than a width of the gate conductor. A self-aligned contact is formed adjacent to the sidewall spacer of the gate structure and is electrically isolated from the gate conductor by the partial dielectric cap and the sidewall spacer.

Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

Abstract: A radiation detector has a photoelectric conversion element array having a light receiving unit and a plurality of bonding pads; a scintillator layer stacked on the photoelectric conversion element array; a resin frame formed on the photoelectric conversion element array so as to pass between the scintillator layer and the bonding pads away from the scintillator layer and the bonding pads and so as to surround the scintillator layer; and a protection film covering the scintillator layer and having an outer edge located on the resin frame; a first distance between an inner edge of the resin frame and an outer edge of the scintillator layer is shorter than a second distance between an outer edge of the resin frame and an outer edge of the photoelectric conversion element array; the outer edge and a groove are processed with a laser beam.

Abstract: An electronic device provided with a package housing a stacked structure formed by dies of semiconductor material, which have a respective integrated circuit and a respective top surface, which extends in a horizontal plane, and are stacked on one another in a vertical direction, transverse to the horizontal plane, and staggered parallel to the same horizontal plane. Provided at a first portion of the top surface is a first plurality of contact pads, and provided at a second portion of the top surface is a second plurality of contact pads. The first portion is covered by a overlying die, and the second portion is exposed and freely accessible. At least some of the contact pads of the first plurality are electrically coupled to internal through silicon vias traversing a substrate of the overlying die to put overlapping dies in electrical contact.

Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

Abstract: A low-cost conductive carrier element provides structural support to a light emitting device (LED) die, as well as electrical and thermal coupling to the LED die. A lead-frame is provided that includes at least one carrier element, the carrier element being partitioned to form distinguishable conductive regions to which the LED die is attached. When the carrier element is separated from the frame, the conductive regions are electrically isolated from each other. A dielectric may be placed between the conductive regions of the carrier element.

Abstract: One embodiment of the present invention is a semiconductor device at least including an oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film therebetween. The oxide semiconductor film has a spin density lower than 9.3×1016 spins/cm3 and a carrier density lower than 1×1015/cm3. The spin density is calculated from a peak of a signal detected at a g value (g) of around 1.93 by electron spin resonance spectroscopy. The oxide semiconductor film is formed by a sputtering method while bias power is supplied to the substrate side and self-bias voltage is controlled, and then subjected to heat treatment.

Abstract: A method for manufacturing a wavelength conversion member includes: forming a phosphor layer on a base body including phosphor particles and oxide particles affixed to surfaces of the phosphor particles; and forming a cover layer covering the surfaces of the phosphor particles and surfaces of the oxide particles continuously, and having a same oxide material as the oxide particles. A wavelength conversion member includes: a base body, a phosphor layer disposed on the base body and including phosphor particles and oxide particles affixed to surfaces of the phosphor particles; and a cover layer covering the surfaces of the phosphor particles and surfaces of the oxide particles continuously, and including a same oxide material as the oxide particles.

Abstract: An LED leadframe or LED substrate includes a main body portion having a mounting surface for mounting an LED element thereover. A reflection metal layer serving as a reflection layer for reflecting light from the LED element is disposed over the mounting surface of the main body portion. The reflection metal layer comprises an alloy of platinum and silver or an alloy of gold and silver. The reflection metal layer efficiently reflects light emitted from the LED element and suppresses corrosion due to the presence of a gas, thereby capable of maintaining reflection characteristics of light from the LED element.

Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a semiconductor substrate. A first structure and a second structure are respectively disposed on the semiconductor substrate and connected to each other. The second structure includes a limiting layer disposed on the upper surface of the semiconductor substrate, a first polysilicon layer disposed conformally on the limiting layer and the semiconductor substrate, and a second polysilicon layer disposed conformally on the first polysilicon layer. A ridge of the second polysilicon layer is disposed near an edge of the second structure beside the first structure, vertically aligned with the limiting layer and defined as a limiting block.

Abstract: A semiconductor device includes a transistor including a source region, a drain region, and a gate electrode. The gate electrode is disposed in a first trench arranged in a top surface of the semiconductor substrate. The device further includes a control electrode. The control electrode is disposed in a second trench arranged in the top surface of the semiconductor substrate. The second trench has a second shape that is different from a first shape of the first trench.

Abstract: A method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a gate layer over the gate dielectric layer, wherein the gate layer is formed in a conformal manner. The method includes forming a dummy gate layer over the gate layer.

Abstract: Methods for manufacturing semiconductor light-emitting devices and semiconductor light-emitting devices having a high radiating performance and can include a metallic laminate substrate, a semiconductor light-emitting chip and a transparent resin. The metallic laminate substrate can include a cavity so as to be able to accurately mount the light-emitting chip, and also can structures to efficiently radiate heat generated from the light-emitting chip. The transparent resin to encapsulate the semiconductor light-emitting chip in the cavity can include various wavelength converting materials. Additionally, the light-emitting devices can be manufactured in manufacturing processes similar to conventional light-emitting devices.

Abstract: Embodiments of a silicon carbide (SiC) device are provided herein. In some embodiments, a silicon carbide (SiC) device may include a gate electrode disposed above a SiC semiconductor layer, wherein the SiC semiconductor layer comprises: a drift region having a first conductivity type; a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is disposed only partially below the gate electrode, wherein a sheet doping density in the pinch region is less than 2.5×1014 cm?2, and wherein the pinch region is configured to deplete at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region.