Patents Examined by G. Ozaki
  • Patent number: 4549912
    Abstract: In the electromigration process, liquid metal inclusions are migrated into or through bodies of semiconductor material by an electrical potential gradient driving force. The method of this invention provides anode and cathode connections generally useful in the practice of electromigration and connections which are especially useful in circumventing the adverse effects of several types of rectifying junctions encountered in the practice of electromigration.
    Type: Grant
    Filed: December 13, 1982
    Date of Patent: October 29, 1985
    Assignee: General Electric Company
    Inventor: Thomas R. Anthony
  • Patent number: 4519850
    Abstract: In a process for the thermo-migration of liquid phases in a temperature gradient, which process starts from a metal coating (2) on a semiconducting substrate (1), the metal coating (2) is applied to a plane substrate surface (11), the temperature gradient is produced, in vacuo, by means of two flat faces (5, 6), which are parallel and can be heated uniformly, and is reversed by lowering the temperature of the warmer face and, at the same time, raising the temperature of the cooler face. The smooth temperature distribution leads to a reduction in the number of process steps, while at the same time yielding good results.
    Type: Grant
    Filed: August 18, 1983
    Date of Patent: May 28, 1985
    Assignee: BBC Brown, Boveri & Company Limited
    Inventor: Petra Kluge-Weiss
  • Patent number: 4517732
    Abstract: A floating-gate tunnel-injection type EEPROM having an excellent quality tunneling insulating layer is fabricated by forming an impurity-doped region under the tunneling insulating layer by diffusion from a neighboring region. The impurity-doped region under the tunneling insulating layer does not have an edge under the tunneling insulating layer, thus ensuring excellent operation of the EEPROM.
    Type: Grant
    Filed: October 4, 1983
    Date of Patent: May 21, 1985
    Assignee: Fujitsu Limited
    Inventor: Yoshihiro Oshikawa
  • Patent number: 4517728
    Abstract: A manufacturing method for an MIS type semiconductor device features in the preferred form a single masking operation used to define source, gate, and drain windows simultaneously in an upper insulating oxide layer disposed over a semiconducting polysilicon layer, the polysilicon layer being separated from the semiconductor substrate by a thin insulating oxide layer serving as the gate oxide. By subsequent deposition of an overall capping nitride layer, followed by selective removal of layers, using relatively low resolution photoresist and portions of the layers themselves as intermediate etching barriers, and by finally converting the polycrystalline layer to an oxide except where it is protected from oxidation by the presence of a nitride stripe over a gate window, the resulting gate electrode is precisely centered between the source and drain windows, and is sealed on all three sides by a protective oxide layer.
    Type: Grant
    Filed: December 8, 1983
    Date of Patent: May 21, 1985
    Assignee: Clarion Co., Ltd.
    Inventor: Morihiro Niimi
  • Patent number: 4516145
    Abstract: A process for forming the openings (vias) in the glass layer of complementary metal oxide semiconductor (CMOS) integrated circuit chips is presented. The pattern of openings is applied to the glass layer using conventional resist/mask techniques. A plasma is used to remove the glass, and the silicon dioxide layer, if there is one, to expose a portion of the N+ and P+ circuit elements. Decreased conductivity of the crystalline lattice structure of the N+ material, caused by exposure to the plasma, appears as an added resistor between the N+ material and the metallization layer. The added resistance is reduced to acceptable levels before the metallization layer is applied by placing the chip in an inert gas atmosphere at an appropriate elevated temperature for an appropriate time.
    Type: Grant
    Filed: August 31, 1983
    Date of Patent: May 7, 1985
    Assignee: Storage Technology Partners
    Inventors: Jenq S. Chang, Tung S. Chang
  • Patent number: 4514894
    Abstract: In a semiconductor integrated circuit device composed of insulated gate field-effect transistors, the improvement comprises the fact that insulated gate field-effect transistors having gate insulating films of substantially equal thicknesses are arranged on a principal surface of a semiconductor substrate in the shape of a matrix. Gate input columns of the transistors are formed of polycrystalline silicon layers, and some of the transistors are enhancement type, while others are depletion type. Further, the respective transistors are formed by the self-alignment technique which employs the polycrystalline silicon layers as a diffusion mask, and the depletion type transistors are formed by implanting impurity ions opposite in the conductivity type to the substrate into selected areas of the surface of the substrate. Thus, a read only memory in a MOS-IC chip has its occupying area reduced remarkably.
    Type: Grant
    Filed: January 3, 1984
    Date of Patent: May 7, 1985
    Assignee: Hitachi, Ltd.
    Inventor: Hiroto Kawagoe
  • Patent number: 4514752
    Abstract: A displacement compensating module is disclosed wherein a blocking article, such as a polyimide tape, is disposed between an epoxy composition and the back surface of a substrate and between the epoxy composition and the inner surface of a cap for blocking the movement of the epoxy composition into a gap area during the manufacture of the module. An electronic module comprises a substrate, an integrated circuit chip disposed on the substrate, a cap disposed over and enclosing the chip and the substrate, a heat dissipator disposed between the cap and the chip for carrying away the heat dissipated by the chip, and an epoxy composition secured to the back surface of the substrate for sealing the module, and specifically, the chip within the module from harmful external influences. The boundary of a gap is defined by the edge of the substrate and the inner surface of the cap.
    Type: Grant
    Filed: April 10, 1984
    Date of Patent: April 30, 1985
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Engel, Douglas H. Strope, Thomas E. Wray
  • Patent number: 4510676
    Abstract: A method for making a lateral PNP transistor simultaneously with an NPN transistor and the resultant device wherein a first mask defines a base-width by the resistor implant for a P-type resistor and a second mask is overlaid asymmetrically on said first mask to partially cover the collector. At the same time that the NPN extrinsic base contact is made, P-type dopants are introduced in the areas exposed by the first and second masks to provide an emitter and a collector contact for the PNP transistor.
    Type: Grant
    Filed: December 6, 1983
    Date of Patent: April 16, 1985
    Assignee: International Business Machines, Corporation
    Inventors: Narasipur G. Anantha, Santosh P. Gaur, Yi-Shiou Huang, Paul J. Tsang
  • Patent number: 4511413
    Abstract: The new process makes it possible to produce stable buried Zener diodes in large-sized wafers where slow ramping of diffusion temperatures is required to avoid crystal damage and other adverse effects. The process includes an initial deep diffusion of p type dopant carried out in two separate steps. In the first step, a diffusion of p dopant is made and is partially driven in. Thereafter, a second diffusion of p dopant is made over the first diffusion and both diffusions are further driven in to the required degree. The Zener diode is completed by still further diffusions including an n dopant diffusion to establish a sub-surface breakdown junction with the first two p dopant diffusions. The first two p dopant diffusions use the same mask window, and preferably are made during the isolation diffusion sequence for the wafer.
    Type: Grant
    Filed: October 5, 1983
    Date of Patent: April 16, 1985
    Assignee: Analog Devices, Incorporated
    Inventors: Ralph C. Tuttle, Richard S. Payne
  • Patent number: 4509249
    Abstract: A method for fabricating an isolation region in a semiconductor substrate that produces neither a "bird's beak" nor a "bird's head". A smooth substrate surface is provided, which is preferable for multi-layered wiring. The packing density of devices in a bipolar IC circuit can be increased. A sharp-edged isolation groove having a U-shaped cross-section is made by reactive ion etching. The inner surface of the isolation groove is coated by an insulating film. Then the groove is buried with polycrystalline semiconductor material. The polycrystalline material which is deposited on the surface of the substrate is etched off. At the same time the polycrystalline material in the groove is also etched to a specific depth from the surface. An insulating film is then deposited so as to again fill the groove. Then the substrate surface is polished or etched to provide a flat surface.
    Type: Grant
    Filed: September 23, 1983
    Date of Patent: April 9, 1985
    Assignee: Fujitsu Ltd.
    Inventors: Hiroshi Goto, Akira Tabata
  • Patent number: 4509996
    Abstract: A method of making a channel substrate buried heterostructure InP/(In,Ga)(As,P) laser avoids the need to use two separate stages of epitaxial growth by using a channel in a (100) surface substrate 1 extending in the [011] direction with {111}B sides. This allows the channel to be made before the growth of an (In,Ga)(As,P) blocking layer 3 which can be grown under conditions which do not require the use of a mask to prevent nucleation on the channel sides. The same technique is also applicable to the manufacture of a terraced substrate laser incorporating a blocking layer.
    Type: Grant
    Filed: June 24, 1983
    Date of Patent: April 9, 1985
    Assignee: International Standard Electric Corporation
    Inventors: Peter D. Greene, Stephen E. H. Turley
  • Patent number: 4508579
    Abstract: Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from and are integral with a silicon pedestal therefor. Both PNP and NPN transistors may be made by diffusing appropriate dopant material into opposing vertical walls of a protrusion so as to form the emitter and collector regions. The protrusions themselves are formed by anisotropically etching the silicon using submicron insulating studs as a mask. The studs are formed using sidewall technology where a vertical sidewall section of a layer of insulating material is residual to a reactive ion etching process employed to remove the layer of insulating material.
    Type: Grant
    Filed: March 30, 1981
    Date of Patent: April 2, 1985
    Assignee: International Business Machines Corporation
    Inventors: George R. Goth, Shashi D. Malaviya
  • Patent number: 4507846
    Abstract: Gate electrodes for respective n channel and p channel transistors are disposed on a semiconductive layer over an oxide layer. A portion of the semiconductive layer existing between the gate electrodes is removed so that the thickness of the semiconductive layer between the gate electrodes is less than that of the semiconductive layer under the gate electrode.
    Type: Grant
    Filed: October 20, 1983
    Date of Patent: April 2, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Junichi Ohno
  • Patent number: 4507157
    Abstract: A light emitting diode and a method for the manufacture thereof is described. The diode may be formed by liquid phase epitaxial growth from a single melt including p and n conductivity type dopants. The p conductivity type layer grows first followed by the n conductivity layer.
    Type: Grant
    Filed: February 9, 1984
    Date of Patent: March 26, 1985
    Assignee: General Electric Company
    Inventor: James D. Oliver, Jr.
  • Patent number: 4504333
    Abstract: A semiconductor device wherein an oxide film constituting a field region is buried in a semiconductor substrate to make the surface of the field region flush with the top surface of an element region, which is characterized in that another insulating film is buried between the oxide film and the element region. Said another insulating film allows the formation of a larger contact hole.A method for manufacturing such a semiconductor device which is characterized in making use of V-grooves formed in a lift-off process.
    Type: Grant
    Filed: June 4, 1982
    Date of Patent: March 12, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Kei Kurosawa
  • Patent number: 4503600
    Abstract: A process for manufacturing a buried gate field effect transistor having a small effective gate length, which process enables precise control of the threshold voltage. First, a compound semiconductor crystal having a first impurity region as a source region, a second impurity region as a drain region and a channel layer buried inside the compound semiconductor crystal is prepared by a conventional process. A V-shaped groove is then formed with an etching solution having high selectivity toward the crystal face in the gate region of this compound semiconductor crystal. Onto the inner wall surface of the V-shaped groove, a metal likely to form an alloy type of Schottky junction with the compound semiconductor is vapor-deposited. The resultant structure is heated, while measuring the threshold voltage, to form an alloy type of Schottky junction and for use of this junction as a gate electrode.
    Type: Grant
    Filed: February 15, 1983
    Date of Patent: March 12, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki
    Inventors: Riro Nii, Nobuyuki Toyoda, Akimichi Hojo
  • Patent number: 4504332
    Abstract: This invention provides a method for manufacturing a bipolar transistor which comprises steps of selectively forming in the surface of a semiconductor substrate an embedded layer of a conductivity type opposite to that of the substrate, covering the substrate with an insulating layer doped, at the surface thereof with an impurity in the superficial region thereof, removing by etching the insulating layer to form an opening portion through which part of the embedded layer is exposed, simultaneously forming by epitaxial growth a single-crystal semiconductor layer of the same conductivity type as that of the embedded layer on the embedded layer at the opening portion and a polycrystalline semiconductor layer on the insulating layer, diffusing by heating the impurity in the insulating layer into the polycrystalline semiconductor layer to provide a conductivity type opposite to that of the single-crystal semiconductor layer, and successively forming an internal base region and an emitter region in the single-cryst
    Type: Grant
    Filed: May 3, 1982
    Date of Patent: March 12, 1985
    Assignee: VLSI Technology Research Association
    Inventor: Kazuyoshi Shinada
  • Patent number: 4503599
    Abstract: Herein disclosed is a field effect transistor fabricating method comprising: the step of forming a surface portion of a semiconductor substrate with an impurity region for a channel; the step of forming a first material layer, which has a width substantially equal to that of a gate electrode, in such a position on said semiconductor substrate and is to be formed with said gate electrode, a second material layer, which has a width larger than that of said first material layer, above said first material layer, and source and drain regions by an ion implantation using said first and second material layers thus formed as a mask; the step of forming source and drain electrodes in contact with said source and drain regions; the step of forming a third material layer, which has a selectivity with said first material layer in its etched characteristics, on the semiconductor body thus far prepared by the foregoing steps; the step of forming at least an aperture by removing said first material layer in a state using sa
    Type: Grant
    Filed: January 28, 1983
    Date of Patent: March 12, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Kiichi Ueyanagi, Susumu Takahashi, Yasunari Umemoto, Michiharu Nakamura
  • Patent number: 4504328
    Abstract: A first growth melting solution which has been used for the growth of a first layer is first replaced with a third melting solution and then with a second growth melting solution for the growth of a second layer. Using the third melting solution of a composition intermediate the first and second melting solutions effectively suppresses supersaturate or unsaturation of the solute during replacement of the melting solutions.
    Type: Grant
    Filed: September 20, 1983
    Date of Patent: March 12, 1985
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ryoichi Hirano, Hirofumi Namizaki, Wataru Susaki, Toshio Tanaka
  • Patent number: 4502204
    Abstract: A method of manufacturing insulated gate thin film field effect transistors is disclosed in which first and second closely adjacent anodic oxidation electrodes are formed on an electrically insulating substrate, and a semiconducting layer is formed on the insulating substrate and the first and second anodic oxidation electrodes. An anodic oxidation of the semiconducting layer is performed, utilizing the first and second anodic oxidation electrodes, to form an oxide layer on the semiconducting layer. The oxide layer is then patterned to form a gate insulator and the semiconducting layer is patterned to expose a portion of each of the first and second anodic oxidation electrodes. The exposed portions of the first and second anodic oxidation electrodes are patterned to form source and drain electrodes, respectively.
    Type: Grant
    Filed: June 15, 1984
    Date of Patent: March 5, 1985
    Assignee: Citizen Watch Company Limited
    Inventors: Seigo Togashi, Kanetaka Sekiguchi