Abstract: A method for fabricating a semiconductor device is disclosed which includes a step of forming contact holes in insulating films on a substrate, forming a silicate glass layer containing an impurity over the entire surface, and performing the phosphorus getter treatment using POCl.sub.3 at a high temperature. Even when the phosphorus getter treatment is performed after the formation of the contact holes, the substrate or electrodes exposed through the contact holes may not be reduced in thickness or damaged. The impurity may be diffused into the substrate from the silicate glass layer through the contact holes.

Abstract: A pair of narrow channel IGFET devices having separate insulated gate electrode structures formed over narrow channel regions of a substrate flanking a central enhancement region. Methods of forming the narrow channel regions using a single photolithography step and forming separate gate electrode structures overlying each using alternative processes, each generally involving two photolithography steps, are set forth.

Abstract: This invention significantly reduces the problem of undesired lateral diffusion of P type dopants into the P type active area. A thin oxide/nitride sandwich is formed on the surface of a semiconductor wafer and patterned to serve as a mask defining the to-be-formed active areas. An N type dopant implant is performed on the surface of the wafer to establish the desired field inversion threshold voltage. The wafer is then oxidized, with the oxide/nitride sandwich preventing oxide growth in the active areas. A layer of photoresist is applied to the wafer and patterned to expose the to-be-formed P well. That portion of the oxide exposed by the photoresist is removed, as is that portion of the substrate within the to-be-formed P well which contains N type dopants. P type impurities are then applied to the wafer. The photoresist is then removed and the P type dopants are diffused with little oxide growth to provide a P well having the desired dopant profile.

Abstract: An insulated-gate field-effect transistor is disclosed which is particularly suitable for forming high-frequency transistors for a common source circuit configuration.

Abstract: Shallow uniform impurity diffusion regions in a semiconductor substrate can be formed through the steps of forming an insulating film having a window on the semiconductor substrate, forming a semiconductor layer on the insulating film and semiconductor substrate exposed at the window, and diffusing a specified impurity from this semiconductor layer into the semiconductor substrate with the melt of semiconductor layer by a high energy beam such as a laser.Simultaneously, the melted semiconductor layer is recrystallized and is used as a contact electrode having a low resistance and extending from the impurity diffusion region. Diffusion of the impurity into the semiconductor layer, which is the impurity diffusion source, can be performed at the time of forming the semiconductor layer or after the formation of the semiconductor layer.

Abstract: Disclosed is a method of producing a semiconductor device, comprising forming an oxidation-resistive insulating film having one or more openings on a semiconductor substrate, forming an impurity-doped polysilicon pattern in at least the opening of the insulating film by using a mask substantially equal in size to the opening, forming a silicon oxide film on the exposed surface of the polysilicon pattern by thermal oxidation, removing the insulating film, and depositing a conductive material and, then, patterning said conductive material layer for forming an interconnection electrode layer insulated from the polysilicon pattern by the silicon oxide film.

Abstract: A dielectrically isolated region of a monocrystalline substrate, which has a <100> orientation, has a drain region of a field effect transistor (FET) in a surface having a (100) crystal orientation with the drain region being of opposite conductivity to the conductivity of the substrate. A gate channel extends into the substrate from the drain region and is surrounded at its upper end by the drain region. An enlarged recess extends into the substrate beneath the gate channel and has its walls of opposite conductivity to the conductivity of the substrate to form a source region and a plate of a capacitor when the FET is part of a storage cell. The source region has its upper end surrounded by the gate channel.

Abstract: A method for completing the discharge of a primary electrochemical cell in which the discharge has prematurely ceased or has significantly diminished. A primary electrochemical cell to which the method of the invention is applicable includes a plurality of anode and cathode structures arranged in alternation, and an electrolytic solution. Each of the anode structures and the electrolytic solution includes a component subject to consumption by chemical action within the cell during discharge. The anode and cathode structures are connected to external electrical terminals of the cell by way of metal tabs and metal bus bar assemblies.

Abstract: The subject invention conserves memory real estate by employing ROM cells which are FETs or non-FETs depending upon the programming. Each cell comprises a gate, a source and drain region and provision for connections to bit and word lines. Programming is achieved by a mask which permits doping of the source and drain regions to comprise FETs for the cells indicative of one state of logic while precluding doping of the source and drain regions to complete the channel in the cells comprising the other state of logic. Also, the FETs are fabricated, their contacts extending linearly between bit lines which are preferably diffused lines, and the word line making direct contact with gates of the linear cells. The process simplifies the number of steps required to manufacture the FETs and non-FETs by simply providing the programming after the basic cells are formed. Such unprogrammed structures may be inventoried and simply programmed i.e.

Abstract: In the formation of a thin film device, integrity of the semiconductor-insulator and semiconductor-conductor interfaces is preserved by depositing layers of insulator, semiconductor, and conductor in successive sequence under continuous vacuum. In a preferred embodiment, the method minimizes contamination exposure of the critical interfaces between semiconductor and gate insulator and semiconductor and source-drain contacts of a thin film transistor.

Abstract: An improved contact hole in a method of producing a semiconductor device by forming a silicon dioxide insulating layer by a chemical vapor deposition method on a semiconductor substrate, forming a contact hole in the insulating layer diffusing phosphorus or boron impurities into a portion of the insulating layer around the contact hole, heating the substrate to cause plastic flow of the insulating layer; and forming a conductive layer on the insulating layer, wherein the portion of the insulating layer containing a high concentration of phosphorus or boron plastically flows during the heating step.

Abstract: A luminescent or laser diode having a pn-junction surrounding an internally limited luminescent surface area and limiting current flow in the diode is produced by etching a select semiconductor substrate so as to produce a mesa dimensioned accordingly to the required luminescent surface area and without interruption epitaxially depositing and structuring required individual semiconductor material layers on the surfaces of the substrate and mesa to achieve the diode.

Abstract: P-type isolation regions, which surround an island of an n-type epitaxial layer, are formed by providing a p-type dopant at a part of the surface of a p-type silicon substrate. After growing the layer a p-type dopant is also provided at the surface of the layer opposite the part of the substrate surface where the dopant is provided. The dopants are diffused into the layer until the p-type regions meet. To inhibit diffusion of the p-type dopant during epitaxial growth, an n-type dopant having a lower diffusion coefficient than that of the p-type dopant is provided at the part of the substrate surface before providing the epitaxial layer. Formation of the isolation regions can be carried out simultaneously with the formation of p-type regions of a circuit element, for example a transistor, in the islands.

Abstract: A conductor bit line for a dynamic random access memory (RAM) structure is formed of a material selected from the group consisting of polycrystalline silicon and a metal silicide, polycrystalline silicon and a conductive metal, and polycrystalline silicon, a metal silicide, and a conductive metal with the polycrystalline silicon contacting at least a portion of the drain region of the field effect transistor of each of a plurality of cells of the RAM structure via a self-aligned contact. When the selected material is polycrystalline silicon and a metal silicide, the conductor bit line is continuous.

Abstract: Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.

Abstract: A method for manufacturing a semiconductor device having a high breakdown voltage and a high reliability, comprises (a) forming on a semiconductor substrate an insulating layer having a diffusion window; (b) forming an impurity-doped poly-silicon layer on the insulating layer and on that portion of the semiconductor substrate which is exposed through the diffusion window; (c) forming an undoped poly-silicon layer on the impurity-doped poly-silicon layer; (d) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer and undoped poly-silicon layer, thus diffusing the impurity from the impurity-doped poly-silicon layer into the semiconductor substrate through the diffusion window and converting the undoped poly-silicon layer to a silicon oxide layer; (e) forming on the silicon oxide layer an oxidation-resisting mask layer in a desired pattern; and (f) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer, silicon oxide layer and mask l

Abstract: A non-volatile memory storage cell utilizing a single vertical junction field-effect transistor is fabricated by a method, which is compatible with the fabrication of MOSFET interface and logic circuits on the same chip. Assembly of a multi-dielectric stack, which contains the non-volatile element, is accomplished late in the process to avoid degradation of the non-volatility characteristics.

Abstract: The specification discloses a process and apparatus for forming a layer of mercury cadmium telluride of predetermined composition on the surface of a selected substrate by first providing a crystal growth melt comprising mercury, cadmium, and tellurium in a vertically-oriented crystal growth chamber. The melt comprises 33.33 mole percent or more of mercury and is maintained at a predetermined temperature above the liquidus temperature thereof. A condensing means is provided atop the crystal growth chamber in order to condense vapors of mercury which escape from the melt and to return this condensed mercury to the melt, to thereby maintain the melt at a constant composition. The substrate is contacted with this crystal growth melt for a predetermined period of time while cooling the melt below its liquidus temperature at a predetermined rate sufficient to cause the crystal growth of the layer of mercury cadmium telluride on the substrate to a desired thickness.

Abstract: A semiconductor structure and particularly a high-speed VLSI self-aligned Schottky Metal Semi-Conductor Field Effect Transistor having a relatively high operating frequency and low series resistance, predicated upon very controllable small structure geometries made by the growth of oxide bumper insulators on either side of the schottky barrier. The oxide bumpers width is relatively thicker than the depth of the initial silicon dioxide layer on the substrate surface thereby providing effective separation of the gate from the source and drain respectively. Accordingly, spatial separations between the self-aligned gate-and-drain and gate-and-source can be relatively very closely controlled by varying the doping level of an intermediate polysilicon layer thereby providing controllable differential polysilicon oxidation rates for the bumpers. Thus, the series resistance can be controlled to be relatively low thereby providing a VLSI SASMESFET device that can be operated at relatively high speeds.

Abstract: A method for simultaneously patterning-over field oxide, gate oxide, and sidewall oxide--high conductivity metal-silicide electrode metallization for semiconductor integrated circuits involves (1) formation of an unpatterned polycrystalline silicon (polysilicon) layer everywhere on the exposed surface of all the oxides, (2) formation of a patterned photoresist layer on the polysilicon layer, (3) deposition of a layer of the metal-silicide over all exposed surfaces, (4) removal of the patterned photoresist layer to lift off metal-silicide, and (5) oxidation of only exposed portions of the polysilicon layer to form silicon dioxide. The polysilicon layer can be originally doped, so that the doped silicon dioxide can then be removed (without removing undoped silicon dioxide) by means of an etchant which attacks the dopant.