Abstract: Closely-spaced conductors can be used in a semiconductor integrated circuit such as an MOS read only memory or ROM formed by a process compatible with standard N-channel silicon gate manufacturing methods. Address lines and gates are polysilicon strips, and output and ground lines are defined by elongated N+ regions. To allow the spacing between adjacent polysilicon address lines to be closer, alternate rows employ first or second level polysilicon which can even overlap if necessary. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", such as by ion implanting through the polysilicon gates and thin gate oxide.

Abstract: A metal-gate MOS read only memory or ROM array is formed by a process compatible with N-channel silicon gate manufacturing methods for circuits peripheral to the array on the same chip. The ROM is programmed at the time the metal level of contacts and interconnections, is patterned. Address lines and gates are metal in the array, and output and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by patterning the metal to cover the gate or not. After metal patterning, the array is ion implanted through exposed gate oxide in the gates not covered by metal so that degradation is prevented.

Abstract: The occurrence of pyramidal protrusions on the surface of GaAs and GaAlAs p-n junction wafers produced by a multislice liquid phase epitaxy process is avoided by slow cooling to a specified quenching temperature or below. The pyramidal protrusions are constituted of the silicon which is the amphoteric dopant used in these semiconductors. Pyramids are not formed if the epitaxial reactor is cooled at a rate of 1.degree. Celsius to 3.degree. Celsius per minute to a temperature less than about 140.degree. Celsius before the wafers are moved to the cool portion of the reactor and then further cooled to room temperature.

Abstract: An air blast type slag cut-off device for steel converter, adapted for jetting compressed air or gas from a nozzle toward the tap hole of the steel converter to force the slag coming out of the tap hole back into the steel converter. The device has a shut-off valve disposed at a portion of the high-pressure gas pipe just upstream from and in the close proximity of the nozzle. The high-pressure gas pipe and an operating fluid supply pipe for operating the shut-off valve are connected to respective sources through a common rotary joint or through independent flexible hoses, so that the steel converter can be tilted smoothly while maintaining the fluid communication between the pipes and respective sources. The time lag of jetting of the air or gas from the nozzle is minimized thanks to the reduced length of the passage between the shut-off valve and the nozzle.

Abstract: In the electromigration process, liquid metal inclusions are migrated into or through bodies of semiconductor material by an electrical potential gradient driving force. The method of this invention provides anode and cathode connections generally useful in the practice of electromigration and connections which are especially useful in circumventing the adverse effects of several types of rectifying junctions encountered in the practice of electromigration.

Abstract: A technique is described for the preparation of buried channels of arbitrary conductivity type in a semiconductor device or integrated circuit containing oxide moats in an epitaxial surface layer. By following a specific sequence of process steps, two mask layers are obtained from a single mask alignment step which permits adjacent regions in the substrate to be doped to different conductivity and type, if desired, prior to the growth of the epitaxial layer. The resulting epitaxial layer has an irregular surface pattern reflecting the shape of the buried structures to faciliate ready alignment with the mask pattern necessary for the production of oxide moats. The resulting structure has a channel buried under the oxide moat region which is used to inhibit the formation of parasitic channels or create a desired channel for device purposes.

Abstract: A method of manufacturing a semiconductor device in which an aluminum-containing layer, hereinafter referred to as the aluminum source, is locally provided on a semiconductor body 1,2 of silicon and, in a subsequent diffusion treatment, aluminum is diffused from the aluminium source 3 into the silicon body 1,2, and an aluminum-doped region 4 is formed in the silicon body 1,2, characterized in that, prior to the diffusion treatment, the aluminum source 3 is divided into parts 5 each having an area which is small as compared with the area of the region 4 to be formed, with a mutual distance which is smaller than double the distance over which the aluminum in the diffusion treatment is diffused laterally into the silicon body 1,2, and which parts 5 have an uninterrupted shape and are so small that during the diffusion treatment their uninterrupted shape remains unvaried.

Abstract: A plurality of MOS transistors are formed as an integrated semiconductor device, adjacent transistors sharing a common source/drain region which is created by the edges of inverted regions beneath the gates of the transistors. These gates are first and second level polysilicon, with the second partly overlapping the first. On the opposite ends, the source and drain regions are formed by diffusion using the oxide under the first and second level poly as the diffusion mask.

Abstract: In a semiconductor laser comprising an active layer epitaxially formed on a semiconductor substrate and at least a current limiting layer which defines a current injection region of a stripe shape,the improvement is that said substrate has a terrace part on its principle face,said active layer has two parallel bending parts defining a stripe shape active region facing said current injection region in between andsaid stripe shape active region is disposed with a specified angle to said principle face.

Abstract: A method of fabricating a semiconductor device comprising forming an island-shaped multi-layered structure of oxides and nitrides on the surface of a semiconductor. The multi-layered structure is selectively etched to define diffusion windows for forming a semiconductor structure in the semiconductor surface having a central region of one conductivity type surrounded by another region of a different conductivity type. A second island-like multi-layered structure is formed and is etched for controlling the duration of the etching steps by controlling the amount that the masks lift off from the insulation layers subjected to etching. The etching is carried out by side etching.

Abstract: Disclosed is a method of evolving B.sub.2 O.sub.3 from certain B.sub.2 O.sub.3 containing glass-ceramics by heating the glass-ceramic in the pressure of helium as a carrier or transport gas.

Abstract: Semiconductor devices can be fabricated using as an intermediate manufacturing structure a substrate of one semiconductor with a thin epitaxial surface layer of a different semiconductor with properties such that the semiconductors each have different solubilities with respect to a metal. When a vertical differentiation is used to expose the different materials and the metal is deposited on both and heated, the metal will form a Schottky barrier in one material and an ohmic contact in the other. Where the substrate is gallium arsenide and the epitaxial layer is gallium aluminum arsenide and the metal is tin, a self-aligned gallium arsenide MESFET is formed wherein the tin forms ohmic contacts with the gallium arsenide and a Schottky barrier contact with the gallium aluminum arsenide.

Abstract: In order to form MOSFET structures, a cobalt layer (16) is deposited and sintered, at about 400.degree. C. to 500.degree. C., on a patterned semiconductor wafer having exposed polycrystalline (14) or monocrystalline (11) silicon portions, as well as exposed oxide (15 or 25) portions. The cobalt reacts with exposed surfaces of the silicon portions and forms thereat such compounds as cobalt monosilicide (CoSi) or di-cobalt silicide (C0.sub.2 Si), or a mixture of both. The unreacted cobalt is selectively removed, as by selective etching in a suitable acid bath. A heat treatment at about 700.degree. C. or more, preferably in an oxidizing ambient which contains typically about 2 percent oxygen, converts the cobalt compound(s) into relatively stable cobalt disilicide (CoSi.sub.2).

Abstract: A process for producing a semiconductor device and for minimizing the effects of implanted boron on a silicon dioxide insulator layer is presented. The process includes the using of a silicon nitride film having windows to define the regions of a semiconductor device, such as a bipolar transistor and isolation regions wherein the isolation region and the semiconductor regions are formed by thermal diffusion of boron using a self-alignment production process. A first mask of the silicon nitride film is formed by patterning its in the form of an endless stripe so that the influence of the reaction between the boron and silicon nitride upon the silicon nitride film is considerably reduced as compared with the conventional process. As a result, the problem of low production yield and low reliability of the semiconductor device is solved.

Abstract: An oxide layer is partially formed on an n-type region surrounded by a field oxide region. A base region of a switching transistor is formed in the n-type region using as a mask the oxide layer. Arsenic-doped polysilicon layers are selectively formed simultaneously on the surfaces of the oxide layer and the base region. Using the polysilicon layers as a mask, the emitter and collector regions of an injector transistor and the external base region of a switching transistor are formed in the n-type region and the base region respectively. Arsenic doped into the polysilicon layers is diffused into the base region, so that the collector regions of the switching transistor are self-aligned with the polysilicon layers.

Abstract: A method of manufacturing an SIT or SITL device, comprising simultaneous formation of a gate doping aperture and contact apertures for a source and a drain. Firstly, a gate region is doped through the doping aperture with the contact apertures being covered by a mask. Then, a source region is doped so as to be in self-alignment relation relative to the gate region and a source contact portion is doped so as to be in self-alignment relation relative to the source region and the gate region, whereby the mask alignments are eliminated and packing density is enhanced.

Abstract: Liquid metal inclusions are migrated in a host body of semiconductor material by means of an electrical potential gradient to produce regions of recrystallized single crystal semiconductor material in the host body. The resistivities of the regions and the semiconductor material of the host body will be different and if the conductivity types of the regions and the semiconductor material of the host body are also different, P-N junctions will be formed between the regions and the host body.

Abstract: A method is provided for registering a pattern on a mask plate with a pattern already formed on a semiconductor wafer. A reflector group is provided on the wafer comprising a plurality of reflectors having a predetermined shape, interval and alignment. Two window groups are provided at predetermined positions on the mask plate. Each window group comprises a plurality of windows having a predetermined shape, interval and alignment that corresponds to the shape, interval and alignment of the reflector group. One of the window groups is provided with a staggered phase relationship with the other window group such that when one of the wafer or the mask plate is moved relative to the other, variations in the quantity of light reflected by the reflector group and passed through the respective window groups is used to determine the relative position of the wafer and the mask plate.

Abstract: Disclosed is a method of growing a layer of CdTe on HgCdTe by liquid phase epitaxy. The solution for growth comprises Sn and Hg with a small amount of CdTe. A typical composition is Sn:Hg:CdTe=36:5:0.15 parts by weight. The growth temperature is a function of the amount of CdTe in solution. For the typical composition stated, the growth temperature is about 520.degree. C. The layers were grown on (111)A oriented CdTe substrates. The HgCdTe epilayer with a desired Cd composition is first grown, and an epilayer of CdTe is subsequently grown on the HgCdTe epilayer. The cross-diffusion at the CdTe/Hg.sub.1-x Cd.sub.x Te interface has been as small as 0.3 .mu.m for the thin CdTe epilayer. The first CdTe/HgCdTe heterojunction sensitive to .about.2.8 .mu.m at 77K has been demonstrated.

Abstract: The invention provides a method for fabricating a semiconductor device comprising the steps of: forming an insulating layer on a semiconductor substrate; selectively forming an oxidation preventive film on the surface of said insulating layer; depositing polycrystalline silicon on the entire surface of said substrate including said oxidation preventive film; selectively etching said polycrystalline silicon so as to leave said polycrystalline silicon only around the sides of said oxidation preventive film by an etching method having a directivity perpendicular to the surface of said substrate; ion-implanting an impurity for preventing inversion in said substrate using as a mask said oxidation preventive film and said polycrystalline silicon remaining therearound; and forming a field insulator film including an oxide of said polycrystalline silicon by oxidizing the surface of said substrate. A higher integration and a higher reliability of elements may be attained according to the method of the invention.