Abstract: The present disclosure provides an organic light emitting diode display device including: first to third color filter layers disposed corresponding to red, green, and blue sub-pixels, respectively; and a fourth color filter layer alternately arranged including a color layer having the same color as any one of the first to third color filter layers in a white sub-pixel in each of a plurality of pixels, and having a smaller height than the first to third color filter layers. Additional color filter layers may also be included. The display device of the present disclosure has lower reflectance and enhanced black color expression.

Abstract: A fan-out semiconductor package includes a first connection member having a through hole, a semiconductor chip in the through hole, having an active surface with a connection pad and an inactive surface on an opposing side. An encapsulant encapsulates at least a portion of the first connection member and the semiconductor chip. A second connection member is on the first connection member and the semiconductor chip. The first connection member and the second connection member each include a redistribution layer electrically connected to a connection pad of the semiconductor chip. The interface between the second connection member and the encapsulant is located on a different level from the level of the interface between the second connection member and a redistribution layer of the first connection member or the level of the interface between the second connection member and a connection pad of the semiconductor chip.

Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes: first common electrode lines; gate lines; a gate insulation layer; data lines, the first common electrode lines crossing the data lines to define a plurality of pixel units, each gate line dividing a corresponding pixel unit into two sub-regions, a separate TFT being arranged at each sub-region; second common electrode lines; and a drain electrode pad arranged at each sub-region and a drain electrode connection line for connecting the drain electrode pad to a drain electrode of the TFT. The drain electrode pad, the drain electrode connection line and the drain electrode are arranged at an identical layer. An orthogonal projection of each second common electrode line onto the base substrate overlaps an orthogonal projection of the drain electrode pad onto the base substrate.

Abstract: Embodiments of the present invention provides an array substrate. The array substrate includes a display region and a packaging region. The packaging region includes a plurality of functional layers. And the packaging region further includes: a plurality of through holes running through at least one of the plurality of functional layers and configured to allow a packaging adhesive to enter therein; and a groove formed above at least some of the through holes, wherein, projection areas of the at least some of the through holes onto a base substrate of the array substrate are located within a projection area of the groove onto the base substrate. Embodiments of the present invention further provides a display panel and a display apparatus including the abovementioned array substrate, and a method of manufacturing the abovementioned array substrate.

Abstract: A display device is disclosed including an array substrate including a plurality of pixels arranged in a display region, the display region including a planar region and a curved region, and a sealing layer covering the plurality of pixels and arranged across the display region, wherein the sealing layer includes a first organic insulation layer and a second organic insulation layer, a film thickness of the first organic insulation layer is more than a film thickness of the second organic insulation layer in the planar region, a film thickness of the second organic insulation layer is more than a film thickness of the first organic insulation layer in the curved region, and a hardness of the second organic insulation layer is lower than a hardness of the first organic insulation layer.

Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.

Abstract: A method for depositing a germanium tin (Ge1-xSnx) semiconductor is disclosed. The method may include; providing a substrate within a reaction chamber, heating the substrate to a deposition temperature and exposing the substrate to a germanium precursor and a tin precursor. The method may further include; depositing a germanium tin (Ge1-xSnx) semiconductor on the surface of the substrate, and exposing the germanium tin (Ge1-xSnx) semiconductor to a boron dopant precursor. Semiconductor device structures including a germanium tin (Ge1-xSnx) semiconductor formed by the methods of the disclosure are also provided.

Abstract: An nchMOSFET of a level-raising circuit is arranged in a high voltage junction termination region (HVJT), to be integrated with a parasitic diode formed by an n?-type diffusion region and a second p-type separation region. On a high potential side of the HVJT, a first field plate (FP) also acting as a drain electrode of the nchMOSFET and a second FP also acting as a cathode electrode of a parasitic diode are arranged away from each other. On a low potential side the HVJT, a third electrode also acting as a source electrode of the nchMOSFET is arranged in a planar layout surrounding the periphery of a high potential side region. On an interlayer insulating film, an interval between a first portion of the third FP and a fourth portion of the first FP is larger than an interval between the second and the third FPs.

Abstract: A resistance change element includes first and second electrodes spaced apart from each other, a metal material layer adjacent to the first electrode, an oxide layer adjacent to each of the metal material layer and the first electrode, and a resistance change layer disposed continuously between the second and first electrodes and between the second electrode and the oxide layer. The resistance change layer is made of a metal oxide. The metal material layer is made of a metal or a metal compound. The oxide layer is made of an oxide of the material forming the metal material layer. The first electrode is made of ruthenium, ruthenium oxide, iridium, iridium oxide, platinum, gold, or copper. A free energy of oxide formation of the oxide forming the oxide layer is higher than a free energy of oxide formation of the oxide forming the resistance change layer.

Abstract: A display device includes a plurality of emitting elements corresponding to a plurality of pixels. The emitting element includes a lower electrode, an upper electrode having a light-transmitting property, and a light-emitting layer between the lower electrode and the upper electrode. The lower electrode includes a flat portion and an inclined portion that is inclined obliquely upward and outward from the central area of the flat portion. Both of the flat portion and the inclined portion include a reflective surface respectively. The reflective surface of the flat portion has a light reflectance lower than that of the reflective surface of the inclined portion.

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

Abstract: Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a common plate structure, and a first capacitor dielectric material between the first and second nodes. The second capacitor is vertically displaced relative to the second transistor. The second capacitor has a third node electrically coupled with a source/drain region of the second transistor, a fourth node electrically coupled with the common plate structure, and a second capacitor dielectric material between the first and second nodes. Some embodiments include memory arrays having 2T-2C memory cells.