Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.

Abstract: An optical assembly and a display device are disclosed. In an embodiment an optical assembly includes a common carrier, a plurality of first chip groups, each first chip group comprising at least two similar luminescence diode chips, a plurality of second chip groups, each second chip group comprising at least two similar luminescence diode chips, wherein the first and second chip groups are arranged planar along a regular grid of first unit cells on a main surface of the common carrier and an optical element arranged downstream of the first and second chip groups with respect to a main radiation direction, wherein the luminescence diode chips of the different chip groups are configured to emit electromagnetic radiation of different wavelength characteristics.

Abstract: The present invention relates to OLED devices and stacks for OLED devices that include a symmetric emissive-layer architecture. In one embodiment, the present invention relates to an emissive stack having three layers, wherein the top and bottom layers emit light in the same or similar color region while the middle layer emits light in a different color region than the other two layers. In such an embodiment, the three layers are in contact with each other with no other layers in between. The symmetric emissive-layer architecture of the present invention can be used to improve the color stability of OLED devices.

Abstract: Display panel and display device are provided. The display panel includes fingerprint recognition units, a substrate, drive circuits, and organic light-emitting units. A distance between two adjacent drive circuits in each drive circuit group is less than a distance between two adjacent drive circuits in two adjacent drive circuit groups along a first direction. The drive circuits from a first row to an i-th row is a first drive circuit, and the drive circuits from a j-th row to an M-th row is a second drive circuit. A first direction component, along the first direction, of each of vias that correspond to at least a portion of the first drive circuit pointing to a first corresponding electrically-connected anode, and a second direction component, along the first direction, of each of vias that correspond to at least a portion of the second drive circuit pointing to a second corresponding electrically-connected anode, are opposite components.

Abstract: According to a flexible light-emitting device production method of the present disclosure, after an intermediate region (30i) and flexible substrate regions (30d) of a plastic film (30) of a multilayer stack (100) are divided from one another, the interface between the flexible substrate regions (30d) and a glass base (10) is irradiated with lift-off light. The multilayer stack (100) is separated into a first portion (110) and a second portion (120) while the multilayer stack (100) is in contact with a stage (210). The first portion (110) includes a plurality of light-emitting devices (1000) which are in contact with the stage (210). The light-emitting devices (1000) include a plurality of functional layer regions (20) and the flexible substrate regions (30d). The second portion (120) includes the glass base (10) and the intermediate region (30i).

Abstract: According to a flexible OLED device production method of the present disclosure, after an intermediate region (30i) and flexible substrate regions (30d) of a plastic film (30) of a multilayer stack (100) are divided from one another, the interface between the flexible substrate regions (30d) and a glass base (10) is irradiated with laser light. The multilayer stack (100) is separated into a first portion (110) and a second portion (120) while the multilayer stack (100) is in contact with a stage (212). The first portion (110) includes a plurality of OLED devices (1000) which are in contact with the stage (212). The OLED devices (1000) include a plurality of functional layer regions (20) and the flexible substrate regions (30d). The second portion (120) includes the glass base (10) and the intermediate region (30i).

Abstract: A method of forming a buried power rail for transistor devices is provided. The method includes forming an adjacent pair of transistor devices on a substrate, wherein the adjacent pair of transistor devices is separated by a gap distance, GD, filled by a fill layer. The method further includes forming a dielectric plate between the adjacent pair of transistor devices by removing a portion of the fill layer, and forming a protective liner on each of the adjacent pair of transistor devices. The method further includes forming a sidewall spacer on each of the protective liners, and forming a buried power rail on the dielectric plate and between the sidewall spacers. The method further includes removing a portion of the sidewall spacers above the buried power rail to form spacer bars on the dielectric plate, and forming a power rail cap on the buried power rail and spacer bars.

Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element.

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

Abstract: A display apparatus comprises a first substrate comprising a first external surface and a first internal surface; a second substrate having a second external surface and a second internal surface facing the first internal surface of the first substrate; and a display unit disposed between the first and second substrates and comprising an array of pixels. The first substrate comprises a first side connecting the first external surface and the first internal surface. In a cross section perpendicular to the first external surface, the first side comprises a first straight region and a first curved region located between the straight region and the first internal surface. The second substrate comprises a second side connecting the first external surface and the first internal surface. The second side comprises a second straight region and a second curved region located between the straight region and the second internal surface.

Abstract: A synthetic diamond heat spreader that includes a first layer of synthetic diamond material forming a base support layer and a second layer of synthetic diamond material disposed on the first layer of synthetic diamond material and forming a diamond surface layer. The diamond surface layer has a thickness equal to or less than a thickness of the base support layer. The diamond surface layer has a nitrogen content less than that of the base support layer. The nitrogen content of the diamond surface layer and the diamond support layer is selected such that the thermal conductivity of the base support layer is in a range 1000 W/mK to 1800 W/mK and the thermal conductivity of the surface support layer is in a range 1900 W/mK to 2800 W/mK.

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. The vertically alternating sequence is divided into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches therethrough. Each neighboring pair of alternating stacks is laterally spaced apart from each other by a respective backside trench. The sacrificial material layers are replaced with multipart layers.

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.

Abstract: Provided is a semiconductor package of a package on package (PoP) type having an improved electromagnetic wave shielding property. The semiconductor package includes: a first sub-package including a first package base substrate on which a first semiconductor chip is mounted, and an electromagnetic wave shielding member having a top portion and side portions respectively at a top surface and side surfaces of the first sub-package, wherein a groove space extends inward from a bottom surface of the first sub-package; and a second sub-package including a second package base substrate in the groove space and on which a second semiconductor chip is mounted, wherein the second sub-package is connected to the first sub-package through an inter-package connection terminal attached to a first package connection pad at a bottom surface of the groove space of the first sub-package.

Abstract: A MEMS device and methods of forming are provided. A dielectric layer of a first substrate is patterned to expose conductive features and a bottom layer through the dielectric layer. A first surface of a second substrate is bonded to the dielectric layer and the second substrate is patterned to form a membrane and a movable element. A cap wafer is bonded to the second substrate, where bonding the cap wafer to the second substrate forms a first sealed cavity comprising the movable element and a second sealed cavity that is partially bounded by the membrane. Portions of the cap wafer are removed to expose the second sealed cavity to ambient pressure.

Abstract: A semiconductor device includes a base substrate, a protruding structure on the base substrate, a porous film on a side surface and an upper surface of the protruding structure, and an air gap between at least a part of the side surface of the protruding structure and the porous film.

Abstract: An array substrate has a display area and a non-display area disposed at a periphery of the display area. The array substrate includes: a base substrate; at least one gate driver on array (GOA) circuit disposed on the base substrate and disposed in the non-display area; a planarization layer disposed on a side of the at least one GOA circuit facing away from the base substrate; and at least one electrostatic protection portion disposed on a surface of the planarization layer facing away from the base substrate and disposed in the non-display area. An orthographic projection of each GOA circuit on the base substrate is located within an outer boundary of an orthographic projection of a corresponding electrostatic protection portion on the base substrate.

Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.

Abstract: A novel thin film encapsulated OLED panel architecture and a method for making the panels with improved shelf life is disclosed. The OLED panel consists of a plurality of OLED pixels; each OLED pixel is individually hermetically sealed and isolated from its neighboring pixels. The organic stack of the OLED pixel is contained within its own hermetically sealed structure, achieved by making the structure on a barrier coated substrate and using a first barrier material as the grid and a second barrier for encapsulating the entire OLED pixel. The first barrier material provides the edge seal while the second barrier disposed over the pixel provides protection from top down moisture diffusion. By isolating and hermetically sealing individual pixels; any damage such as moisture and oxygen ingress due to defects or particles, delamination, cracking etc. can be effectively contained within the pixel thereby protecting other pixels in the panel.