Abstract: A system for managing composed information handling systems includes information handling systems and a composed information handling system of the composed information handling systems, which includes at least one compute resource set, at least one control resource set, and at least one hardware resource set. The system also includes a system control processor that obtains a bare metal communication from a compute resource set indicating a write of data, writes a first copy of the data in a storage resource of the at least one hardware resource set, writes a second copy of the data in a trace volume, generates a backup of the data using the trace volume, and stores the backup in a storage.

Abstract: Methods, computer readable media, and devices for identifying and preventing invalid memory access. A method may include defining a dynamic scope for an operation, receiving a request to allocate a portion of the range of shared memory, allocating a monotonically increasing portion of the range of shared memory such that a subsequent request to allocate memory is allocated a different portion of the range of shared memory, receiving a request to deallocate the allocated portion of the range of shared memory, deallocating the allocated portion of the range of shared memory by protecting the deallocated portion of the range of shared memory from any subsequent access, and in response to an access of the protected deallocated portion of the range of shared memory by one of the one or more threads or processes of the operation, trapping and terminating the one thread or process.

Abstract: Various embodiments described herein provide for a memory sub-system read operation or a memory sub-system write operation that can be requested by a host system and involves performing a multi-level (e.g., two-level) pointer dereferencing internally within the memory sub-system. Such embodiments can at least reduce the number of read operations that a host system sends to a memory sub-system to perform a multi-level dereferencing operation.

Abstract: A data management method includes receiving, by a management server, a first request, determining, based on an identifier of a first user in the first request, whether a shadow tenant bucket associated with the identifier of the first user exists, and if the shadow tenant bucket associated with the identifier of the first user exists, storing, in the shadow tenant bucket associated with the identifier of the first user, an acceleration engine image (AEI) that the first user requests to register, where a shadow tenant bucket is used to store an AEI of a specified user, and each shadow tenant bucket is in a one-to-one correspondence with a user.

Abstract: Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and control logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a read inline encryption engine (IEE) connected to the memory interface, wherein the read IEE is configured to decrypt encrypted data read from the memory; a key selector configured to determine a read memory region associated with the memory read request based upon a read address where the data to be read is stored, wherein the read address is received from the address and control logic; and a key logic configured to select a first key associated with the determined read memory region and provide the selected key to the read IEE.

Abstract: Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.

Abstract: Examples of the present disclosure describe systems and methods for sharing memory using a multi-ring shared, traversable and dynamic database. In aspects, the database may be synchronized and shared between multiple processes and/or operation mode protection rings of a system. The database may also be persisted to enable the management of information between hardware reboots and application sessions. The information stored in the database may be view independent, traversable, and resizable from various component views of the database. In some aspects, an event processor is additionally described. The event processor may use the database to allocate memory chunks of a shared heap to components/processes in one or more protection modes of the operating system.

Abstract: A storage device for providing an improved security function may include a nonvolatile memory device, a position information generator generating first position information indicating a first geographical position of the nonvolatile memory device when an authentication request is input, a user information storage storing user information for accessing the nonvolatile memory device, the user information including second position information, and an access controller obtaining, in response to an authentication request provided from an external host, the first position information from the position information generator, and disposing of data stored in the nonvolatile memory device depending on whether the second position information included in the user information matches the first position information.

Abstract: Security credentials associated with a first account maintained by a database system are authenticated. Based on authenticating the security credentials, a user interface element is provided to enable sharing of customer data associated with the first account with an application. A request to share customer data with the application is received. Based on the request, third-party data that is accessible by the first account is identified. The third-party data corresponds to a second account maintained by the database system. The second account corresponds to a third-party data provider. The application is enabled to access cloud data associated with the first account based on the request. The cloud data comprises the customer data and the third-party data.

Abstract: Framed event access in an ordered event stream (OES) storage system is disclosed. Events can be written to one or more segments of an OES and can have an inherent write sequence. Segments can be parallel segments. Reading events from parallel segments can result in a read sequence that does not match the write sequence. This mismatch can be more severe as segment length increases, as event density disparities increase, as access times diverge for different segments, or for numerous other reasons. Event framing can compartmentalize divergence between the write and read sequence. In an aspect, readers in the several segments of the OES can be constrained to read within a frame defined by frame boundaries until all readers have reached the frame boundary, then can advance to a next frame. The restriction can act as a pseudo-synchronization of readers that can mitigate difference between write and read sequences.

Abstract: A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a memory device of the set, wherein the memory device stores multiple bits per memory cell; sending a message to a host system indicating a reduced capacity of the set of memory devices; receiving from the host system a message to continue at the reduced capacity; and updating the set of memory devices based on the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of the memory device.

Abstract: A processing device of a memory sub-system is configured to receive a request to add content to a system data structure, wherein a first plurality of blocks of a common pool of blocks are allocated to the system data structure and a second plurality of blocks of the common pool of blocks are allocated to user data; determine whether user data has been written to the second plurality of blocks of the common pool of blocks within a threshold amount of time; and responsive to determining that the user data has not been written to the second plurality of blocks within the threshold amount of time, allocate a block from the second plurality of blocks of the common pool of blocks allocated to user data to the first plurality of blocks of the common pool of blocks allocated for the system data structure.

Abstract: A list of a first type of tracks in a cache is generated. A list of a second type of tracks in the cache is generated, wherein I/O operations are completed relatively faster to the first type of tracks than to the second type of tracks. A determination is made as to whether to demote a track from the list of the first type of tracks or from the list of the second type of tracks.

Abstract: Provided are a computer program product, system and method for data storage volume record management for application-level recovery in accordance with the present description. In one embodiment, logical volume movement is addressed when performing enterprise application recovery. In one embodiment, a host-based recovery product in accordance with the present description, can detect logical volume movement from one physical device to another and proactively prevent application level recovery that potentially may result in data loss. In one embodiment, a time-based capturing of pairings of logical and physical volume identifiers or descriptors within storage configuration records and sub-records are used to surgically recover volumes of an application from enterprise level protection copy of physical media. This history of pairings facilitates many types of logical volume to physical media remapping, such as the regular migration of data to replacement storage controllers which can occur at various times.

Abstract: A storage device includes a memory and a controller. The controller controls the memory such that, in response to a request for a first read operation on the memory while a first write operation is performed on the memory, the first write operation is suspended, and the first read operation is performed, the suspended first write operation is resumed after the first read operation is completed, and second write operation subsequent to the first write operation is performed on the memory after the resumed first write operation is completed. The controller throttles an amount of data communicated to the memory device for the second write operation or for a second read operation subsequent to the first read operation, based on a frequency that the first write operation is suspended.

Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.

Abstract: A combination default write-blocking system may include a host computer. The host computer may include at least one general storage device storing program instructions for a blocking driver assembly and a host processor configured as the blocking driver assembly while executing the program instructions for the blocking driver assembly. A connection interface device physically separate from the host processor, and the connection interface device is configured to be operatively coupled to the host processor and to a protected storage device physically separate from the general storage device, receive a communication from the blocking driver assembly, and establish communication between the protected storage device and the host processor after receiving the communication from the blocking driver assembly. The blocking driver assembly is further configured to communicate with the connection interface device and conditionally allow a host computer process to alter data stored on the protected storage device.

Abstract: Deploying client-specific applications in a storage system utilizing redundant system resources, including: identifying a redundant controller in the storage system, wherein the storage system includes at least a first controller and the redundant controller; and executing one or more applications on the redundant controller, wherein the one or more applications are executed in a container.

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information are provided. The method may include: sending internal information of the memory device to a host device, to allow the host device to store the internal information of the memory device in a memory within the host device as host side table information at the host device; generating and storing multiple entries of at least one address mapping control table into a random access memory (RAM) as at least one portion of device side table information at the memory device; determining at least two physical addresses associated with at least two logical addresses according to the at least one address mapping control table; and reading data from the NV memory according to the at least two physical addresses.