Abstract: Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.

Abstract: A method for performing a copyback procedure is described. The method includes determining to move first encoded data from a first location in a memory die to a second location. In response to determining to move the first encoded data from the first location to the second location, a starting seed, which is associated with the first location, is combined with a destination seed, which is associated with the second location, to produce a combined seed. Based on the combined seed, the method determines a pseudorandom sequence based on the combined seed and a pseudorandom sequence table, wherein the pseudorandom sequence table maps seed values to pseudorandom sequences and the determined pseudorandom sequence maps to the combined seed in the pseudorandom sequence table. The method further combines the first encoded data with the pseudorandom sequence to produce second encoded data for storage in the second location.

Abstract: Techniques and mechanisms for capturing an image of processor state at one node of multiple nodes of a multi-processor platform, where the processor state includes some version of data which the node retrieved from another node of the platform. In an embodiment, a disruption of power is detected when a processor of a first node has a cached version of data which was retrieved from a second node. In response to detection of the disruption, the data is saved to a system memory of the first node as part of an image of the processor's state. The image further comprises address information, corresponding to the data, which indicates a memory location at the second node. In another embodiment, processor state is restored during a boot-up of the node, wherein the state includes the captured version of data which was previously retrieved from the second node.

Abstract: A memory allocation method and apparatus is disclosed. The method includes: obtaining unoccupied mirrored memory in an initial mirrored memory, where the initial mirrored memory is indicated by a mirrored memory address range that is provided by an BIOS of a computer system to the an OS of the computer system during initialization of the OS; performing detection on data requiring memory allocation; and when detecting that the data is data to be stored in mirrored memory, allocating, from the unoccupied mirrored memory, the mirrored memory to the data to be stored in the mirrored memory. The memory allocation method can accurately find the mirrored memory, and allocating the mirrored memory to the data that needs to be stored in the mirrored memory. Therefore, this method ensures usage efficiency of the limited mirrored memory.

Abstract: The present invention provides a flash memory controller, where the flash memory controller includes a read-only memory, a processor and a cache, the read-only memory stores a program code, and the processor executes the program code to perform access a flash memory module. When the processor receives first data from a host, the processor stores the first data into a region of the cache, and the processor builds or updates a binary tree according to the first data, wherein the binary tree is used when the processor receives a read command from the host.

Abstract: A TLB receives an access request with respect to a first address and access authorization assigned to the request from an arithmetic operation control unit, translates the first address to a second address, determines the suitability of the access authorization, and outputs the access request with respect to the first address when the access authorization is not suitable. An MMU receives the access request with respect to the first address output from the TLB, translates the first address to the second address, determines the suitability of the access authorization, and outputs a notification of access prohibition to the arithmetic operation control unit when the access authorization is not suitable.

Abstract: Embodiments of the present disclosure relate to method, device and computer program product for data backup. In accordance with embodiments of the present disclosure, if a file is migrated between a first machine and a second machine, a data migration module compares the file with files already stored in the second machine, so as to only migrate modified and/or added data chunks in the files to the second machine. In this way, the performance of data migration has been improved.

Abstract: A request to add content to a system data structure can be received. A first set of blocks of a common pool of blocks are allocated to the system data structure and a second set of blocks of the common pool of blocks are allocated to user data. A determination can be made as to whether a garbage collection operation associated with the first set of blocks of the common pool allocated to the system data structure satisfies a garbage collection performance condition. Responsive to determining that the garbage collection operation satisfies the garbage collection performance condition, a block from the common pool can be allocated to the first set of blocks allocated to the system data structure.

Abstract: Techniques described herein generally include methods and systems related to cache partitioning in a chip multiprocessor. Cache-partitioning for a single thread or application between multiple data sources improves energy or latency efficiency of a chip multiprocessor by exploiting variations in energy cost and latency cost of the multiple data sources. Partition sizes for each data source may be selected using an optimization algorithm that minimizes or otherwise reduces latencies or energy consumption associated with cache misses.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.

Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

Abstract: An embodiment of a semiconductor apparatus may include technology to provide placement option information to a host in response to a host query, and create a namespace to access a persistent storage media based on host-provided isolation granularity information. Other embodiments are disclosed and claimed.

Abstract: A common memory device shared by a first processor and a second processor is provided. The common memory device includes a memory cell array including a first memory region allocated for the first processor and a second memory region allocated for the second processor, a refresh masking information storage circuit configured to store refresh masking information indicating whether a refresh is performed on at least one of the first and second memory regions, and a refresh circuit configured to selectively perform the refresh on the first memory region and the second memory region according to the refresh masking information.

Abstract: Aspects include prefetching a plurality of high-level information, high-level metadata, low-level metadata, and low-level information including a plurality of components associated with a monitored entity for disaster recovery. A subsequent instance of the high-level information, the high-level metadata, and the low-level metadata is requested. The subsequent instance of the high-level information is fetched based on detecting a change in the high-level metadata. A subsequent instance of one or more of the components of the low-level information corresponding to one or more changes in the low-level metadata is fetched for updating a plurality of disaster recovery data of the monitored entity in a persistent database.

Abstract: In general, embodiments of the technology relate to a method and system for storing and reading data from persistent storage. More specifically, embodiments of the technology relate to a method and system for storing data in persistent storage, where the data written to the persistent storage is not immediately accessible in the persistent storage (i.e., during the inaccessibility period). In such instances, embodiments of the technology provide a method and system to enable the storage system to service read requests for the data using a primary cache entry table (PCET) and an overflow table.

Abstract: An apparatus includes a control circuit and a cache memory with a plurality of regions. The control circuit receives a first and a second access request to access the cache memory. In response to determining that the first access request is from a particular processor core, and that the first access request is associated with a particular cache line in the cache memory, the control circuit stores the first access request in a cache access queue. In response to a determination that the second access request is received from a functional circuit, and that the second access request is associated with a range of a memory address space mapped to a subset of the plurality of regions, the control circuit stores the second access request in a memory access queue. The control circuit arbitrates access to the cache memory circuit between the first access request and the second access request.

Abstract: Provided are techniques for destaging pinned retryable data in cache. A ranks scan structure is created with an indicator for each rank of multiple ranks that indicates whether pinned retryable data in a cache for that rank is destageable. A cache directory is partitioned into chunks, wherein each of the chunks includes one or more tracks from the cache. A number of tasks are determined for the scan of the cache. The number of tasks are executed to scan the cache to destage pinned retryable data that is indicated as ready to be destaged by the ranks scan structure, wherein each of the tasks selects an unprocessed chunk of the cache directory for processing until the chunks of the cache directory have been processed.

Abstract: The present invention provides systems and methods for data storage. A hierarchical storage management architecture is presented to facilitate data management. The disclosed system provides methods for evaluating the state of stored data relative to enterprise needs by using weighted parameters that may be user defined. Also disclosed are systems and methods evaluating costing and risk management associated with stored data.

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

Abstract: An apparatus and method are described for mediate pass through and shared memory page merging. For example, one embodiment of a method comprises: generating a page identifier (PI) for each of a set of guest memory pages, wherein equivalent PIs indicate that the corresponding memory pages are the same; upon detecting that a first guest memory page and a second guest memory page have PIs that are equal, merging the first and second guest memory pages into a single memory page; detecting that the first guest memory page is to be used for a direct memory access (DMA) operation; and responsively unmerging the first and second guest memory pages.