Abstract: Syllables are recognized in voice data obtained from an input voice signal. Character arrays are used to represent the types and time frames of syllables with which the voice data are compared.

Abstract: An adder circuit that has an encoded carry input, where a bit position weight of the carry input is two, allows the adder circuit to selectively concurrently add a data value of two to a first and a second input data operand of the adder circuit. The adder circuit is also able to add the first and second input data operands with a second carry input that is not encoded. A recoded multiplier combines two partial product calculations into one calculation during only a first partial product calculation operation by using the adder circuit. Partial product calculations are reduced in number during a multiply operation of a data processor.

Abstract: A multi-function ALU (arithmetic/logic unit) for use in digital data processing facilitates the execution of instructions in parallel, thereby enhancing processor performance. The proposed apparatus reduces the instruction execution latency that results from data dependency hazards in a pipelined machine. This latency reduction is accomplished by collapsing the interlocks due to these hazards. The proposed apparatus achieves performance improvement while maintaining compatibility with previous implementations designed using an identical architecture.

Abstract: An apparatus for rapidly switching between output display frames using a shared frame identification memory is disclosed which has particular application to high resolution graphics for animation. Through a plurality of comparison circuitry, the apparatus enables a frame to be displayed during the clock cycles when the frame identification memory is read and during the clock cycles when the frame identification memory is provided with input, thereby, allowing a frame identification memory to be shared by two output display memories. As a result the rapid switching between output display frames sufficient for animation may be achieved with less hardware.

Abstract: A programmable logic controller (PLC) device for effecting arithmetic operations of a sequential program by a microprocessor (1). The PLC device comprises a periodic signal generating circuit (2) for generating an interruption signal at a predetermined time interval, an input circuit (7) for receiving an external input signal, and circuits for effecting filter processing by reading a signal output by the input circuit at a predetermined time interval in response to the interruption signal. Since the filtering processing is effected by the microprocessor, a time constant of a filter can be changed by a program and can be also changed for each signal.

Abstract: Optical computing cells or logic cells are constructed of two or more spatial light rebroadcasters (SLR's). Data or information images in the form of light are written into and read from the SLR's with the SLR's being controlled to process the data in a desired manner. The logic cells can be used generally to construct optical computers and are particularly adapted to the construction of optical subsystems for a digital optical computer. In addition, the logic cells can be used for performing masking, interface, intermediate storage and other operations within an optical computer. Cells made up of only SLR's can be used directly for many applications. The cells also can be modified by the internal or external addition of other optical elements for routing light between or among SLR's of the cells, processing and/or blocking light as the light passes between SLR's of the cells. Such modifications and adaptations complement cells made up only of SLR's to form a family of optical logic cells.

Abstract: A method for displaying characters on a screen or printer, particularly kanji characters. The structure of the character is represented by stems and counters, both vertical and horizontal, the counters being the spaces between stems. The character is then adjusted to be displayed. Either the horizontal or vertical counters are grouped into a first chain of counters. The non-integral counter widths of this chain are adjusted in relation to the other counter widths within the chain, selected counter widths being made equal to others within the chain in order to most faithfuly reproduce the desired character. The remaining horizontal or vertical counters, if any, are also grouped into one or more series of chains which are also adjusted, chain by chain. Then the other set of counters are adjusted in the same way.

Abstract: A method for navigating between and within application programs resident in a computer system provides easy access to the programs and data within the programs. Two or more windows may be optionally linked together in an arbitrary sequence to form a chain. A user may invoke a function resident in the computer system to directly access windows in the chain in a sequence determined by the order in which the user opens the windows in a given session. The method for traversing between windows in the chain involves a uniform, short procedure dependent on positioning of a pointing cursor within an active window and, for example, pressing a mouse button. Further access to data within any application program is available by following a procedure which, although slightly different from that used to navigate between programs, is still uniform and short when compared with that normally used to traverse application programs.

Abstract: A graphic processing system including a main memory for storing a program and information corresponding to pixels, a main processor for effecting an execution processing of a program transferred from the main memory or from an external device so as to control the system, display/output devices such as a CRT device and a printer for outputting graphic information attained by controlling pixels arranged in a plurality of dimensions, a frame buffer for storing information corresponding to pixels outputted to the display/output devices, and a graphic processor for receiving a command and parameter information transferred from the main memory and/or the main processor, for generating character and graphic data in accordance with a predetermined processing procedure and for performing a transfer control including an execution of a drawing processing to transfer generated data through first and second address buses and first and second data buses to the main memory and/or the frame buffer, respectively.

Abstract: The multiplier-adder in the Galois fields can have parameters applied to it, i.e. it is possible to choose the Galois field CG(2.sup.m) in which the polynomial operations are performed, with m at most equal to N, N being predetermined by the designer. The multiplier-adder is made up of a decoder (10) organized as N identical elementary cells receiving the generator polynomial G(m:0) and supplying the generator polynomial without its least significant bit G(m-1:0) and a polynomial marking the degree of the generator polynomial, DG(m-1:0), and a computing matrix (20) organized as N columns of identical elementary cells receiving the polynomials A, B and C of the Galois field CG(2.sup.m) and supplying a polynomial result P=(A*B).sub.modulo G +C. The multiplier-adder has usage for example as a digital signal processing processors for error detecting and correcting encoding and decoding using BCH or RS codes.

Abstract: There are provided a backup version page table in a storage for providing a correspondence between the pages of a database and the slots in a database storage medium in which the contents of pages to be recovered, if necessary, are stored; a current version page table for providing a correspondence between pages updated by a transaction and slots in the database storage medium wherein the updated contents of the pages are stored; and a journal file for recording various system journals; wherein the updated page contents are stored in the database stored medium at the slots not-used at that time and found with reference to the backup version page table and the current version page table.

Abstract: In a data processing device for processing table data, a memory is adapted for storing the table data lined up in matrix shape. The data of each of the table elements can be displayed with the line item name and the row item name in a display unit having a small number of lines so that the table data may have a corresponding identification for a row and a line.

Abstract: A shadow generation method and apparatus that employs a depth buffer technique to increase the speed of calculation of visible shadows. The system employs pipelined processors to determine visible objects and shadows generated by those objects for one or more light sources. The technique determines whether a shadow exists at a given pixel by evaluating the parity of the number of intersections between shadow polygons and a line of sight extending from the viewpoint. Pipeline processing is introduced to speed the process to result in rapid evaluation of a large number of objects and associated shadows. An alternate embodiment is presented which retains many of the speed advantages but allows the use of processors other than pipelined processors. Determination of the effect of a shadow on a given point is further speeded by indexing the shadow affect resulting in a quantized shadow correction value that reduces the processing requirements.

Abstract: A computer output system having a first full screen bitmapped memory, a second full screen bitmapped memory, logic circuitry for providing input signals for writing information to be displayed by an output device to each position of the first memory, logic circuitry for storing in the second memory the positions of each position of the first memory to be written to the output device, and logic circuitry for comparing the signal stored at each position of the first memory and the signal stored at the same position of the second memory to determine whether information at the position is to be written to the output device.

Abstract: A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system (10) which comprises a control and timing circuit (18), a microprogram store (20) and a multiplier circuit (34). The multiplier circuit (34) may comprise a rectangular aspect ratio multiplier circuit (40) having an additional ADDER INPUT to enable the repeated evaluation of first order polynomials to evaluate polynomial expansions associated with each mathematical function. A constant store (28) is used to store predetermined coefficients for the polynomial expansion associated with each mathematical functions. The microprogram store (20) is used to store argument transformation routines, polynomial expansions and result transformation routines associated with each mathematical function.

Abstract: Apparatus and method for reconstructing non-quantized adaptively transformed voice signals are shown to include noise shaping wherein the spectral envelope is scaled prior to generating bit allocation and energy substitution which is achieved after dequantization by generating the spectral envelope information for each block of transform coefficients based upon side information, generating transform coefficients which correspond to transform coefficients which were not de-quantized and for substituting the generated transform coefficients into said blocks; and transforming said blocks of de-quantized transform coefficients and generated transform coefficients from said transform domain into said time domain.

Abstract: An image processing system has sixteen processing assemblies provided by transputers which each have a memory and a processor. An infra-red television camera supplies signals representing different areas of the field of view to respective different ones of the processing assemblies. The assemblies also receive external signals from other sources and are interconnected with one another by a line which enables synchronization between the assemblies. Each processor processes only that information in its memory and provides output signals representative of the respective area of the field of view.

Abstract: A speech recognition apparatus has a speech input unit for inputting a speech; a speech analysis unit for analyzing the inputted speech to output the time series of a feature vector; a candidates selection unit for inputting the time series of a feature vector from the speech analysis unit to select a plurality of candidates of recognition result from the speech categories; and a discrimination processing unit for discriminating the selected candidates to obtain a final recognition result. The discrimination processing unit includes three components in the form of a pair generation unit for generating all of the two combinations of the n-number of candidates selected by said candidate selection unit, a pair discrimination unit for discriminating which of the candidates of the combinations is more certain for each of all .sub.n C.sub.

Abstract: The automatic access of processes running on a computer is made possible by the display of graphic icons corresponding to the processes. A user can manipulate data in a table and then select a view function which results in the display of icons corresponding to potentially valid processes for the data in the table. By marking data in the table, the user causes only those icons corresponding to valid processes valid for the marked data to be displayed in a manner which allows selection of the icons. If the user then selects one of these icons, the system automatically makes the operation corresponding to the selected icon for the marked data. The user may then place the result of the operation on the display screen by dragging the selected icon to the desired location on the screen.

Abstract: An arithmetic circuit for calculating and accumulating absolute values of differences between first and second numerical values having a predetermined bit length and represented by 2's compliment notation is provided by a first inverter for inverting the second numerical value to produce an inverted value; a first adder receiving the first numerical value and the inverted numerical value and generating a sum as a first addition result; and a selector receiving the first addition result from first adder and an inverted addition result from the first adder via a second inverter and outputting a selected value based on the sign of the first addition result. A correcting value generating circuit generates a correcting value based on the sign of the first addition result. A second adder receives the selected value, the correcting value and a delayed addition result and generates a sum as a second addition result, which is output to a first delay circuit.