Abstract: Dynamically allocating cache in a multi-tenant infrastructure includes monitoring cache usage for multiple workloads in a multi-tenant processing infrastructure to determine a workload phase. A baseline performance level per workload is determined. The baseline performance level is dependent upon the workload phase. The workloads for each tenant are categorized based on cache utilization and the cache is allocated to each workload based on the baseline performance level, cache utilization, and system wide cache capacity.

Abstract: Disclosed herein are system, method, and computer program product embodiments for cache partitioning to accelerate concurrent workload performance of in-memory databases. An embodiment operates by storing a first bitmask, associating the first bitmask with a first processor core, setting a subset of the bits of the first bitmask, wherein the subset of the bits of the first bitmask represents a first portion of shared last-level cache, and wherein any part of the first bitmask excluding the subset of the bits of the first bitmask represents a second portion of the lowest-level cache, and disallowing eviction of any cache line in the second portion of the lowest-level cache by the first processor core.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.

Abstract: A system and method is provided for probabilistic defense against remote exploitation of memory. In certain embodiments, the system comprises one or more processors, read and execute (RX) portions of memory, read and write (RW) portions of memory, execute only (XOM) portions of memory, and one or more programs stored in the memory. The one or more programs include instructions for maintaining all pointers to RX memory instructions in XOM memory. In addition, the one or more programs include instructions for preventing all direct references to RX memory in RW memory by forcing pointers in RW memory to reference XOM memory first, which then references RX memory instructions.

Abstract: A method and a storage system are provided for implementing enhanced solid state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing Dynamic Random Access Memory (DRAM), and at least one 5 non-volatile memory, for example, Phase Change Memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND Flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.

Abstract: A semiconductor memory device includes a first plane including a memory cell array, a second plane including a memory cell array, a control circuit configured to control operations performed on the first and second planes separately and independently, and first register for storing a condition value related to a condition of an operation to be performed on a plane. When a first command to store a first condition value in a first address of the first register is received, the control circuit specifies a plane to which the first address has been allocated. When the first plane is specified by the first address, the control circuit determines whether the first plane is in a command receivable state. Then, when the control circuit determines that the first plane is in the command receivable state, the control circuit stores the first condition value in the first address of the first register.

Abstract: The present disclosure relates to a data unit reuse method, where data is stored in a data unit in the form of a data block and the data block has a block ID. The method includes: successively reading each data block in a current data unit to search for a first specific data block whose block ID does not conform to a predetermined order; determining whether at least one data block whose block ID conforms to the predetermined order exists after the specific data block in the current data unit; when it exists, determining that the current data unit has been damaged, and when it does not exist, determining that a data block immediately previous to the specific data block is a data end.

Abstract: A method for hardware assisted data lookup in a storage unit is provided. The method includes formatting data in at least one of a plurality of data formats for storage in the storage unit. The method includes configuring a logic unit with one or more parameters associated with the plurality of data formats and identifying incoming data with the one or more parameters as an instruction for execution.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a memory string including memory cells including first to third memory cells, and a selection transistor connected to the memory cells, and first to third word lines that are connected to gates of the first to third memory cells of the memory string. The memory controller reads data of the first to third memory cells by applying first to third read voltages to the first to third word lines, respectively. The memory controller reads second data by applying a fourth read voltage to the second word line in parallel to processing of decoding first data, obtains likelihood information on the basis of the first data, the second data, and at least one of the third data and the fourth data, and decodes data on the basis of the likelihood information.

Abstract: To prevent an excessive increase of a dirty data amount in a cache memory. A processor acquires storage device information from each of storage devices. When receiving a write request to a first storage device group from a higher-level apparatus, the processor determines whether a write destination cache area corresponding to a write destination address indicated by the write request is reserved. When determining that the write destination cache area is not reserved, the processor performs, on the basis of the storage device information and cache information, reservation determination for determining whether to reserve the write destination cache area. When determining to reserve the write destination cache area, the processor reserves the write destination cache area. When determining not to reserve the write destination cache area, the processor stands by for the reservation of the write destination cache area.

Abstract: A technique accesses a non-resident segment and a resident segment of a segmented de-duplication index, the resident segment being currently loaded into primary memory from secondary storage for data block de-duplication, and the non-resident segment not being currently loaded into the primary memory from the secondary storage for de-duplication. The technique further discovers that a digest of a non-resident digest entry of the non-resident segment and a digest of a resident digest entry of the resident segment are duplicates. The non-resident digest entry includes a first reference to a first location of the secondary storage that holds a first data block copy, and the resident digest entry includes a second reference to a second location of the secondary storage that holds a second data block copy. The technique further performs reconciliation that conforms the non-resident segment and the resident segment of the index to reference only data block copy.

Abstract: An object is divided into SD1 first-level pieces. Each first-level piece is stored in a first-level container on a first-level storage entity. A redundant encoding of the first-level containers is stored in RL1 additional first-level containers on RL1 additional first-level storage entities. On each of the first-level storage entities, the locally-stored first-level container is divided into SD2 local second-level pieces. Each second-level piece is stored in a second-level container on a second-level storage entity of the specific first-level storage entity. Each first-level storage entities contains SD2 plus RL2 second-level storage entities. A redundant encoding of the second-level containers is stored in RL2 additional second-level containers on RL2 additional second-level storage entities.

Abstract: A method, computer program product, and computing system for freeing up cache space includes identifying a portion of cache space for removal from a cache system, thus defining a cache portion to be removed, and ceasing to promote the cache portion to be removed. Data that needs to be relocated within the cache portion to be removed is identified, thus identifying flushable data. The flushable data is relocated to a backend storage system associated with the cache portion to be removed.

Abstract: A storage system and method for thermal throttling via command arbitration are provided. In one embodiment, a storage system is provided comprising a memory and a controller in communication with the memory. The controller is configured to determine whether a temperature of the storage system exceeds a threshold; and in response to determining that the temperature of the storage system exceeds the threshold, pause fetching of new commands from a host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A memory device includes receiving, by a memory module, a first combined signal and a second combined signal from a memory controller and decoding, by the memory module, the first combined signal and the second combined signal to obtain a first chip enable signal, a first address latch enable signal, and a first command latch enable signal. Upon decoding, the first command latch enable signal and the first address latch enable signal are received substantially simultaneously as the first chip enable signal to reduce a setup time.

Abstract: Logical to physical mapping of managed units (“MUs”) of object data in a flash memory system storing MUs that are being created continuously by applications running on a client system is maintained in an extent based tree in DRAM for extents of contiguous MUs and in an override tree in DRAM for individual MUs. Extent mapping data in the extent tree for extents comprises a starting address and a length. Mapping data for individual MUs in the override tree comprises individual pointers from logical addresses to physical addresses. Source erase blocks in flash memory are reorganized asynchronously by iteratively moving individual MUs of an object in order from a source erase block to a free erase block to empty the source erase block and free up associated DRAM.

Abstract: According to one embodiment, an information processing apparatus includes a first memory, a signal generation unit, an integrity check unit, and an access-right update unit. Firmware is stored in the first memory. The signal generation unit is configured to generate a signal when there is access violating access right, to the first memory. The integrity check unit is configured to perform, when the access violating access right is a verification request with respect to a predetermined verification target region, integrity check with respect to the verification target region in response to the signal. The access-right update unit is configured to update access right corresponding to the verification target region, to which the integrity check has been performed.

Abstract: Techniques for performing forward error correction of data to be transmitted over an optical communications channel. The techniques include: receiving data bits; organizing the data bits into an arrangement having a plurality of blocks organized into rows and columns and into a plurality of strands including a first strand of blocks that includes a back portion comprising a first row of the plurality of blocks, and a front portion comprising blocks from at least two different columns in at least two different rows other than the first row of blocks; and encoding at least some of the data bits in the arrangement using a first error correcting code at least in part by generating first parity bits by applying the first error correcting code to first data bits in the front portion of the first strands and second data bits in the back portion of the first strand.

Abstract: A system, computer program product, and computer-executable method for managing flash devices within a data storage environment utilized by an application of one or more applications, wherein the application accesses the managed flash devices through a pool of flash storage provided by the data storage, the system, computer program product, and computer-executable method comprising receiving a data I/O from the application, analyzing the data I/O directed toward the pool of flash storage in relation to the flash devices, and managing the flash devices based on data I/Os directed toward the pool of flash storage by the application.

Abstract: According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.