Abstract: A memory appliance may be provided comprising a processor, a communication interface, a memory, and a region access unit. The memory may be configured in an address space addressable by the processor. The communication interface may be configured to provide the client access to the region of the memory via client-side memory access before initialization of all of the region. A method to create a virtual copy of memory accessible by client-side memory access is also provided. A system may be provided that memory maps at least a portion of a file to a memory region, wherein a virtual address addressable is generated, and the at least a portion of file is accessible through the memory region at the virtual address. The virtual address may be registered with the communication interface, where registration of the virtual address provides client-side memory access to the memory region.

Abstract: A system and method for network traffic management between multiple nodes are described. A computing system includes multiple nodes connected to one another. When a home node determines a number of nodes requesting read access for a given data block assigned to the home node exceeds a threshold and a copy of the given data block is already stored at a first node of the multiple nodes in the system, the home node sends a command to the first node. The command directs the first node to forward a copy of the given data block to the home node. The home node then maintains a copy of the given data block and forwards copies of the given data block to other requesting nodes until the home node detects a write request or a lock release request for the given data block.

Abstract: Virtualization software establishes multiple execution environments within a virtual machine, wherein software modules executing in one environment cannot access private memory of another environment. A separate set of shadow memory address mappings is maintained for each execution environment. For example, a separate shadow page table may be maintained for each execution environment. The virtualization software ensures that the shadow address mappings for one execution environment do not map to the physical memory pages that contain the private code or data of another execution environment. When execution switches from one execution environment to another, the virtualization software activates the shadow address mappings for the new execution environment. A similar approach, using separate mappings, may also be used to prevent software modules in one execution environment from accessing the private disk space or other secondary storage of another execution environment.

Abstract: A system includes reception of an instruction to create a data block associated with a portion of a database table in a non-volatile memory system, creation, in response to the instruction to create the data block, of a file associated with the data block in the non-volatile memory system, where a filename of the file comprises an indication that the data block is a temporary block, creation of an entry in a data block map table indicating that the data block is a temporary block, reception of an instruction to commit the data block, and, in response to the instruction to commit the data block, flush data associated with the data block to the file in the non-volatile memory system, rename the file to remove the indication that the data block is a temporary block, and update the entry in the data block map to indicate that the data block is a committed block.

Abstract: A schedule for refreshing a dynamic random access memory (DRAM). Access commands for a DRAM are queued in a command queue. A microcontroller uses a counter to count how many times a rank of the DRAM is refreshed entirely (whether by a one-time per-rank refresh operation or by a series of per-bank refresh operations). When the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue, the microcontroller repeatedly performs the per-rank refresh operation on the rank. Every refresh inspection interval, the microcontroller decreases the counter by 1.

Abstract: A data processing system implementing a weak memory model includes a plurality of processing units coupled to an interconnect fabric. In response execution of a multicopy atomic store instruction, an initiating processing unit broadcasts a store request on the interconnect fabric to obtain coherence ownership of a target cache line. The initiating processing unit posts a kill request to at least one of the plurality of processing units to request invalidation of a copy of the target cache line. In response to successful posting of the kill request, the initiating processing unit broadcasts a store complete request on the interconnect fabric to enforce completion of the invalidation of the copy of the target cache line. In response to the store complete request receiving a coherence response indicating success, the initiating processing unit permits an update to the target cache line requested by the multicopy atomic store instruction to be atomically visible.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: Techniques for performing forward error correction of data to be transmitted over an optical communications channel. The techniques include: receiving data bits; organizing the data bits into an arrangement having a plurality of blocks organized into rows and columns and into a plurality of strands including a first strand of blocks that includes a back portion comprising a first row of the plurality of blocks, and a front portion comprising blocks from at least two different columns in at least two different rows other than the first row of blocks; and encoding at least some of the data bits in the arrangement using a first error correcting code at least in part by generating first parity bits by applying the first error correcting code to first data bits in the front portion of the first strands and second data bits in the back portion of the first strand.

Abstract: Some embodiments provide a method for a first device to synchronize a set of data items with a second device. The method receives a request to synchronize the set of data items stored on the first device with the second device. The method determines a subset of the synchronization data items stored on the first device that belong to at least one synchronization sub-group in which the second device participates. Participation in at least one of the synchronization sub-groups is defined based on membership in at least one verification sub-group. The first and second devices are part of a set of related devices with several different verification sub-groups. The method sends only the subset of the synchronization data items that belong to at least one synchronization sub-group in which the second device participates to the second device using a secure channel.

Abstract: According to an embodiment, a cache unit includes: a first memory configured to temporarily hold data and an address of the data, a second memory configured to temporarily hold an address of particular data set in advance, and a controller configured to, when an instruction to load the data is made for a first specified address, search for a storage destination of the first specified address, output the data of the first specified address if the storage destination is the first memory, and output the particular data if the storage destination is the second memory.

Abstract: A memory system includes a write buffer, a main memory having a higher latency than the write buffer, and a memory controller. In response to a write request indicating first data for storing at a write address in the main memory, the memory controller adds a new write entry in the write buffer, where the new write entry includes the write address and the first data, and updates a pointer of a previous write entry in the write buffer to point to the new write entry. In response to a write-back instruction, the memory controller traverses a plurality of write entries stored in the write buffer, and writes into the main memory second data of the previous write entry and the first data of the new write entry.

Abstract: The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. The controller is configured to execute a command to transfer data from a latch component to a register file in the controller. The memory device includes an array of memory cells and the latch component is coupled to rows of the array via a plurality of columns of the memory cells. The latch component includes a latch selectably coupled to each of the columns and configured to implement the command to transfer the data. The memory device includes a data line to couple the latch component to the register file to transfer the data. The controller is configured to couple to the data line and the register file to perform a write operation on the transferred data to the register file in the controller.

Abstract: Embodiments provide the ability to configure software backup and restoration procedures on an IHS (Information Handling System) with minimal or no input from a user. Embodiments utilize local monitors on an IHS in order to generate metadata describing the use of software applications installed on the IHS. A remote analytics engine process the metadata received from multiple participating IHSs to generate inputs used by the restoration and backup procedures implemented by the IHS. The metadata generated by an IHS is used to determine valuations for the applications and files installed on the IHS. These valuations may then be utilized to identify files of significant value to the user, which may then be designated for backup by the backup procedures implemented by the IHS. The generated valuations may also be used to select the applications that should be reinstalled in order to restore the IHS to an approximated prior operating state.

Abstract: A method, computer readable medium and apparatus for improving non-uniform memory access are disclosed. For example, the method divides a plurality of stream processing jobs into a plurality of groups of stream processing jobs to match a topology of a non-uniform memory access platform. The method sets a parameter in an operating system kernel of the non-uniform memory access platform to favor an allocation of a local memory, and defines a plurality of processor sets. The method binds one of the plurality of groups to one of the plurality of processor sets, and run the one group of stream processing jobs on the one processor set.

Abstract: Methods, apparatus and articles of manufacture are disclosed to enforce life cycle rules in a modularized virtualization topology using virtual hard disks. An example method includes, in response to a request to access a first virtual hard disk in a virtual computing environment, identifying, with a processor, a life cycle stage. The example method also includes determining, with the processor, whether a condition associated with the life cycle stage applies to the first virtual hard disk. The example method also includes refusing, with the processor, to mount, refusing to dis-mount, mounting or dis-mounting the first virtual hard disk if the condition is satisfied.

Abstract: Systems and methods for handling operation requests in a computing device. The methods comprise: queuing a first I/O operation and first TRIM operation in a first list of operations; analyzing the first TRIM operation for a plurality of block portions of a disk cache to determine a size thereof; estimating a first amount of time to complete the first TRIM operation; comparing the first amount of time to a first threshold value; selectively dividing the first TRIM operation into at least a second TRIM operation for first block portions contained in the plurality of block portions and at least a third TRIM operation for second block portions contained in the plurality of block portions, if the first amount of time is greater than the first threshold value; performing the first I/O operation followed by the second TRIM operation; and queuing the third TRIM operation in a second list of operations.

Abstract: A flash memory control technology with high efficiency, which records a logical page table in a random access memory. The logical pages that have been collected from a data-interspersed block into a destination block of a flash memory are recorded in the logical page table. Without accessing a logical-to-physical address mapping table stored in the flash memory, the physical pages in the data-interspersed block corresponding to the logical pages recorded in the logical page table are regarded as containing invalid data.

Abstract: A technique processes input/output (I/O) requests from a set of host computers. The technique utilizes data storage equipment which includes a set of physical storage drives and storage processing circuitry which accesses the set of physical storage drives. The technique involves storing, by the storage processing circuitry, a set of storage drive objects in main memory. The set of storage drive objects includes a set of zeroed chunk tables. Each storage drive object (i) represents a physical storage drive and (ii) includes a zeroed chunk table which identifies storage chunks of that physical storage drive that have been initialized to zero. The technique further involves receiving, by the storage processing circuitry, I/O requests from the set of host computers, and performing, by the storage processing circuitry, I/O tasks in response to the I/O requests. The I/O tasks include zero on demand operations based on the set of zeroed chunk tables.

Abstract: A non-volatile memory system may include a plurality of dies, where the plurality of dies are configured in a plurality of chip enable groups and at least one of the chip enable groups includes less than a maximum number of dies that may be uniquely identified according to a die selection scheme, where different memory arrays have different capacities and/or include memory elements of different types or technologies, or some combination thereof. One or more virtual die layouts, addressing schemes and mappings, wear leveling schemes, and initialization schemes may be employed for these multi-die configurations.

Abstract: Implementations disclosed herein provide for a storage system including an on-disk read cache and a variety of read cache management techniques. According to one implementation, a storage device controller time-sequentially reads a series of non-contiguous data blocks storing a data sequence in a read cache of a magnetic disk, the data sequence identified by a requested sequence of logical block addresses (LBAs). The controller determines that read requests for the data sequence satisfy at least one predetermined access frequency criterion and, responsive to the determination, the controller re-writes data of the data sequence to a series of contiguous data blocks in the read cache.