Abstract: An apparatus including a printed circuit board (PCB) including a sense resistor; and an integrated circuit (IC) mounted on the PCB, wherein at least a portion of the IC draws current from a power rail, wherein the sense resistor is coupled between the power rail and the IC, wherein the sense resistor is configured to produce a sense voltage in response to the current drawn by the at least portion of the IC, and wherein the IC includes a current sensor configured to generate a signal indicative of the current drawn by the at least portion of the IC based on the sense voltage.

Abstract: The present disclosure discloses a power management circuit, a chip and an upgrade method therefor, and a server. In the circuit, one terminal of a micro controller unit is connected to a control board and a processor of the chip, and the other terminal of the micro controller unit is connected to a power management integrated circuit unit, a voltage conversion unit, and a voltage regulator unit. The micro controller unit receives operation instructions sent by the control board and the processor, stores the operation instructions, reads a power-on/off operation instruction in the operation instructions that is sent by the control board, and sends the power-on/off operation instruction to the power management integrated circuit unit to enable the power management integrated circuit unit performs corresponding control on the voltage conversion unit and the voltage regulator unit to complete a power-on/off operation on the processor.

Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Abstract: Methods and systems for power management are disclosed. The disclosed methods and system for power management may reduce the likelihood of a data processing system failing to meet power budget or other types of goals regarding power consumption, use, and/or provisioning. To reduce the likelihood of the data processing system failing to meet power related goals, the data processing system may include two power managers. An integrated power manager may manage power consumption based on a current-based, fast changing representation of the quantity of power being supplied by the power supplies. In contrast, a system power manager may manage power consumption based on digital representations of the power supplied by the power supplies, which may refresh the digital representations less quickly than the rate at which the analog current based representation is refreshed.

Abstract: A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.

Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.

Abstract: A processor may identify that an external power source has begun powering a computing device. The processor may identify computational data in a volatile memory of the computing device. The processor may determine that the external power source does not have sufficient energy capacity to provide the computing device enough power to process the computational data at a first I/O throttling rate. The processor may increase the first I/O throttling rate to a second I/O throttling rate. The second I/O throttling rate may allow the computational data to be processed by the computing device with the energy capacity of the external power source.

Abstract: The present invention provides a processing circuit, a method, and an electronic device for multiple power supply ports. The processing circuit includes N control modules and a bus. Each control module is correspondingly connected to a power supply port. The communication interface of each control module is connected to the bus. The bus is a one-wire bus and is connected to a power line ground through a resistor. The control modules transmit value signals to the bus. The varied range of a first physical quantity of a bus signal carried by the bus is related to first physical quantities or second physical quantities of all target signals transmitted to the bus. The control module detects the first quantity of the bus signal through the communication interface and adjusts the operating parameter of the connected power supply port according to the varied range of the detected first physical quantity.

Abstract: Methods, systems, and apparatus, including computer-readable media, for environment monitoring and management. In some implementations, information indicating a planned usage level for usage of cloud computing services is accessed by a group of multiple computing environments over a period of time. Usage of cloud computing services is monitored for the group of multiple computing environments. A usage measure indicating an amount of usage of cloud computing services by the group of multiple computing environments is generated over the period of time. A cloud computing usage notification is generated based on the planned usage level and the usage measure. The cloud computing usage notification is provided for presentation by an electronic device.

Abstract: In an example, a computing device includes a non-volatile storage device to store a basic input/output system (BIOS) variable. Further, the computing device includes a BIOS. During a boot process of the computing devices, the BIOS may read the BIOS variable from the non-volatile storage device. Further, the BIOS may detect that an application is to be deployed in the computing device based on the BIOS variable. Furthermore, the BIOS may load an application package from the non-volatile storage device into a volatile storage device and build an advanced configuration and power interface (ACPI) data structure with the application package loaded in the volatile storage device. Further, the BIOS may deploy the application using the ACPI data structure.

Abstract: A power saving system of a battery charger is provided. A control terminal of a first transistor receives a wake-up signal. A counter is connected to a first terminal of the first transistor. The counter determines whether or not a working period of the wake-up signal from the first transistor is larger than a time threshold to output a counting signal. When the counting signal indicates that the working period of the wake-up signal is not larger than the time threshold, the counter and electronic components of an electronic device are turned off, thereby saving power of a battery. When the counting signal indicates that the working period of the wake-up signal is larger than the time threshold, the electronic device is switched from a power saving mode to a normal operation mode. In the normal operation mode, the battery can supply power to the electronic device.

Abstract: A semiconductor device includes clock adjustment circuits, provided to a plurality of functional circuits operating in synchronization with a clock signal respectively for adjusting a delay amount for each functional circuit, and a clock path selection circuit for controlling whether a clock is transmitted to the functional circuits through any one of a plurality of paths included in the clock adjustment circuits respectively. In the semiconductor device, the clock path selection circuit outputs a path instruction signal for instructing switching of a path for transmitting a clock signal in accordance with a change in an operation state of a plurality of functional circuits.

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

Abstract: Methods, systems, and apparatus, including computer-readable media, for automated idle environment shutdown. In some implementations, activity of a server environment is monitored over a period of time. A measure of user-initiated activity of the server environment is determined based on the monitored activity of the server environment over the period of time. The level of user-initiated activity over the period of time is determined to be less than a threshold level. In response to determining that the level of user-initiated activity over the period of time is less than the threshold level, shut down of the server environment is initiated.

Abstract: Aspects of the present invention disclose a method for dynamically adjusting a clock speed of a core of a multicore processor of user equipment. The method includes one or more processors generating a dedicated logical channel from a user device to a multidomain service orchestration layer of a fifth generation (5G) telecom network. The method further includes collecting information of the user device through the dedicated logical channel. The method further includes identifying situational insight of the user device based at least in part on the information of the user device. The method further includes identifying determining a workload forecast of one or more cores of the user device based at least in part on the situational insight. The method further includes identifying determining a recommended central processing unit (CPU) clock speed for a CPU core of the user device based at least in part on the workload forecast.

Abstract: An information processing apparatus includes a first controller and a second controller. The first controller is configured to control an operation of the overall information processing apparatus. The second controller is configured to control an operation of a device. When detecting a trigger of resumption from a power saving mode, the second controller notifies the first controller of the detection of the trigger, and starts to initialize a function corresponding to the trigger.

Abstract: A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.

Abstract: A computing environment includes multiple client devices that may each be configured to serve a particular function within the computing environment. The client devices are each coupled to a client management server that communicates with and manages functions of the client devices. When a client device first boots, the client management server communicates with the client device over a network in order to provision the client device with an enrollment image. Using the enrollment image, a client device can become enrolled with the client management server. Once enrolled, the client management server can provision the client device with a functional operating system image. The functional operating system image can support device applications that require a restricted number of runtime states within the client device. A new functional operating system image is downloaded from the client management server and installed on the client device each time the device is rebooted.

Abstract: An information processing apparatus includes an ensuring circuit configured to maintain an operation of a first storage connected to a first system in a case where a detection unit detects reduction in voltage of a power supply. A control unit is configured to copy at least data necessary for activating the information processing apparatus from a second storage connected to a second system to the first storage in a case where the first storage is set not to store the data necessary for activating the information processing apparatus and a second storage is set to store the data necessary for activating the information processing apparatus.

Abstract: An autonomous driving system having dual secure boot is provided. The autonomous driving system includes: a control system, a host, and a baseboard management controller (BMC). The control system includes a microcontroller, a first flash memory, and a second flash memory. The first flash memory stores first embedded-controller firmware and a first application image file. The second flash memory stores second embedded-controller firmware and a second application image file. When the autonomous driving system is turned on, the microcontroller executes a dual secure boot procedure to execute the first embedded-controller firmware or the second embedded-controller firmware. In response to the microcontroller successfully executing the first embedded-controller firmware or the second embedded-controller firmware, the microcontroller authenticates the first application image file or the second application image file.