Abstract: Provided is a server device which may be stably operated in spite of power loss and a method of operating the same. The server device according to an embodiment of the present invention includes: a host system; a plurality of memory modules; a backplane configured to transmit main power supplied from the host system to the plurality of memory modules; and at least one replaceable battery module connected to the backplane and configured to supply first auxiliary power to the plurality of memory modules, wherein the plurality of memory modules includes a volatile memory, a non-volatile memory; and a memory module controller using the first auxiliary power supplied from the at least one replaceable battery module to maintain data of the volatile memory or flush data of the volatile memory to the non-volatile memory, in response to the power loss occurring in the main power.

Abstract: Techniques are described for performing an automated region build with real time region data. Region data including region identifiers and execution target identifiers for the region may be maintained. When a modification of the region data is detected (or new region data is detected), configuration files corresponding to bootstrapping resources (e.g., at the execution targets) within the region may be obtained. Operations are executed to cause the configuration files to be updated. This may include recompiling or otherwise injecting region data into the configuration files. A region build may be executed to bootstrap resources within the region using the updated configuration files.

Abstract: A TI-ADC circuit and method therefor include the use of first and second level clock generators configured to receive an asynchronous reference clock signal and generate a plurality of first and second clock signals, the second level clock generator including a plurality of clock dividers connected in series, respective ones of the plurality of clock dividers being configured to divide an input clock signal in accordance with a synchronization signal; a plurality of T/H circuits respectively configured to operate in accordance with one of the first clock signals; a plurality of sub-ADCs respectively configured to operate in accordance with one of the second clock signals, thereby to sample an input signal in a time-interleaved manner, wherein for a given clock divider of the plurality of clock dividers, the synchronization signal corresponds to an output clock of a clock divider immediately upstream from the given clock divider.

Abstract: The present application discloses a power supply circuit, a chip and an electronic device. The circuit comprises: a power module, configured to supply power to a computing chip in serial connection; a first power management module, connected with the power module and the computing chip, and configured to supply power to a core of the computing chip according to a voltage provided by the power module; and at least one second power management module, connected with the power module and the computing chip, and configured to supply power to at least one voltage domain of the computing chip according to the voltage provided by the power module correspondingly before the first power management module supplies power to the core.

Abstract: An operating system (OS) software service detects an accessibility change event and takes a snapshot of the accessibility settings before sending and receiving memory-mapped input/output (MMIO) commands with an embedded controller (EC) to establish trust using existing security hardening methods. The software service may send an MMIO command that includes the profile as a payload to the EC. The EC extracts the profile payload and saves it to an NVRAM variable before signaling a basic input/output system (BIOS) during early boot of an available accessibility profile. The EC publishes an accessibility profile presence to a BIOS pre-EFI initialization (PEI) layer, which sends a command to the EC to return the response.

Abstract: The present disclosure discloses a power management circuit, a chip and an upgrade method therefor, and a server. In the circuit, one terminal of a micro controller unit is connected to a control board and a processor of the chip, and the other terminal of the micro controller unit is connected to a power management integrated circuit unit, a voltage conversion unit, and a voltage regulator unit. The micro controller unit receives operation instructions sent by the control board and the processor, stores the operation instructions, reads a power-on/off operation instruction in the operation instructions that is sent by the control board, and sends the power-on/off operation instruction to the power management integrated circuit unit to enable the power management integrated circuit unit performs corresponding control on the voltage conversion unit and the voltage regulator unit to complete a power-on/off operation on the processor.

Abstract: An electronic device includes an authentication unit and a control unit. The authentication unit performs an authentication communication with an external device for determining whether or not the external device is a predetermined device. The control unit requests a second power that is greater than a first power from the external device, in a case where the external device is determined to be the predetermined device and the external device is determined to be a no-additional-cable-required type of power supply device.

Abstract: Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage.

Abstract: A disclosed method for improving latency or power consumption may include (i) receiving, at a power-state processing circuit, a power-state signal indicating whether a processing unit is entering a low-power-state, (ii) transmitting, in response to the power-state signal indicating that the processing unit is entering the low-power-state, a control signal from the power-state processing circuit to a latching circuit, and (iii) storing, by the latching circuit and in response to the control signal, a state of an input/output pad that is coupled to the processing unit. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A system and method are described herein for estimating power usage of various components of a CPU and controlling voltage regulators based on the estimated power usage. The power estimates may be based on digital power meter readings at each component, on voltage information from a voltage regulator, and on other power information. This power information is transmitted over a mesh interconnect disposed throughout the CPU such that power estimation can be accurately calculated and used to control voltage regulators without being limited by external bus speeds. More of the power management processes and components may be disposed on the CPU and connected to the mesh interconnect. These power management processes include various calibrations, adjustments, and limits so as efficiently manage and use the more rapidly processed power estimations.

Abstract: An information processing system includes an execution block computational strength data area, a roofline model data storage unit, a computational strength data acquisition unit, and a performance power control unit. The execution block computational strength data area holds computational strength data of each execution block constituting an arithmetic application that operates in a computer system including a processor and a main storage apparatus. The roofline model data storage unit holds a roofline model corresponding to an operation frequency and the number of cores of the processor, and an operation frequency of the main storage apparatus. The computational strength data acquisition unit acquires computational strength data of each execution block. The performance power control unit controls an operation frequency and the number of cores of the processor and an operation frequency of the main storage apparatus based on the roofline model and the computational strength data of each execution block.

Abstract: A computing device is provided, including a battery, a processor configured to receive electrical power from the battery via a voltage regulator, and one or more additional electronic components configured to receive electrical power from the battery. The computing device may further include a first current detector configured to detect a total battery discharge current. The voltage regulator may be configured to receive a first analog current signal from the first current detector, convert the first analog current signal into first digital current data, and transmit the first digital current data to the processor. The processor may be further configured to determine a difference between the total battery discharge current and an available electric current limit for the battery. In response to at least determining the difference, the processor may be further configured to adjust one or more performance parameters of the processor such that the difference is reduced.

Abstract: A processor in a device is configured to access a power policy for the device, where the power policy indicates a relationship between power consumption by the device and another performance variable of the device. The processor is also configured to produce an operating point for the device based at least in part on the power policy. The processor is also configured to provide information regarding the operating point to a management entity that manages the device.

Abstract: An electronic device (such as an access point) that selectively changes to an alternative or different partition is described. During operation, when the electronic device is in a first power state (such as a lower power state), an integrated circuit in the electronic device may detect or receive an error state or a change instruction. In response, the integrated circuit may change an active partition in the electronic device from a first partition to a second partition. Next, the integrated circuit may transition the electronic device to a second power state (such as a higher power state). Furthermore, a processor in the electronic device (which may be the same as or different from the integrated circuit) may install and execute an operating system of the electronic device in the second partition.

Abstract: The present disclosure relates to a clock distribution method and apparatus in a network. The method performed at a first clock distribution apparatus comprises: determining (S101) whether the first clock distribution apparatus is in a lock state; and transmitting (S102), to a second clock distribution apparatus, a first announce message when the clock distribution apparatus is not in the lock state; wherein the first announce message is generated based on a default configuration about a local clock state of the first clock distribution apparatus. According to embodiments of the present disclosure, the clock distribution apparatus may generate first announce messages based on a local clock state of the clock distribution apparatus. Thus, a downstream apparatus which receives the first announce messages may avoid selecting an unstable/unlocked clock distribution apparatus as the best master, based on the local clock state of the clock distribution apparatus.

Abstract: Systems and methods for generating a power consumption rating include receiving instrumentation data corresponding to a plurality of applications. The received instrumentation data is processed to calculate a relative power consumption value for each application of the plurality of applications. The relative power consumption value for each application is compared and a power consumption rating for each application based on the comparison is generated, thereby providing a visual indicator of power consumption for the applications that can be easily evaluated.

Abstract: An information processing apparatus according to an embodiment of the present disclosure includes: a processor including a first data processor that is configured to perform a piece of first data processing on the basis of a piece of first data to thereby generate a piece of second data; a selector that selects one piece of data from among a plurality of pieces of data including the piece of first data and the piece of second data; an arithmetic processor that is configured to selectively perform one of a plurality of pieces of arithmetic processing, and performs a piece of arithmetic processing selected from among the plurality of pieces of arithmetic processing on the basis of the piece of data selected by the selector; and a supply section that controls supply of electric power to the first data processor in accordance with the piece of data selected by the selector from among the plurality of pieces of data.

Abstract: A dynamic peak power management system may prevent brownouts while improving performance and user experience compared to conventional techniques. A current threshold may be set below the maximum current capability (Imax) of a battery. If the current drawn from the battery exceeds the current threshold repeatedly, then system components may be throttled to decrease their peak power usage. If the current drawn from the battery stays below the current threshold for some time, then system components may be unthrottled to improve performance. This dynamic adaptable technique for managing peak power does not unnecessarily sacrifice performance by preemptively throttling system components to avoid the rare worst-case scenario where power spikes of system components perfectly align in time.

Abstract: Methods, systems, and devices for providing computer implemented services using managed systems are disclosed. To provide the computer implemented services, the managed systems may need to operate in a predetermined manner conducive to, for example, execution of applications that provide the computer implemented services. Similarly, the managed system may need access to certain hardware resources (e.g., and also software resources such as drivers, firmware, etc.) to provide the desired computer implemented services. To improve the likelihood of the computer implemented services being provided, the managed systems may be managed using a subscription based model. The subscription model may utilize a highly accessible service to obtain information regarding desired capabilities (e.g., a subscription) of a managed system, and use the acquired information to automatically configure and manage the features and capabilities of the managed systems by powering and depowering select components.

Abstract: An information handling system includes a memory, and a basic input/output system (BIOS). The BIOS receives a request to map multiple processor cores to multiple integrated memory controllers of a multiple core processor. In response to the reception of the request, the BIOS calculates a different latency for each of the processor cores. Based on the calculated different latency for each of the processor cores, the BIOS assigns mapping priority levels to the processor cores of the multiple core processor. Based on the mapping priority levels, the BIOS maps each of the processor cores to an associated one of the integrated memory controllers. The BIOS stores the map of the processor cores in the memory.