Abstract: A dynamic power monitor for monitoring a power of a block in an integrated circuit is provided. The dynamic power monitor includes an input buffer configured to store first state values corresponding to internal signals of the block according to a first cycle of a clock signal; a power calculator configured to identify first power classification values corresponding to the block according to the first cycle, based on the first state values; and a filter configured to identify a first filtered value of the first power classification values.

Abstract: A semiconductor device includes a power switch control signal generation circuit. The power switch control signal generation circuit configured to generate a power switch control signal for controlling supply of a power supply voltage based on a reset operation and a power-down mode.

Abstract: Systems and methods are provided for adaptively powering an Information Handling System (IHS) using a multimode AC adapter. Information reported by the multimode adapter is utilized to determine whether it supports USB-PD power transmissions and also supports high-power transmissions. The power demand of the IHS is monitored. When the power demand is greater than the USB-PD power levels, the multimode adapter is configured for providing a high-power transmission and a power circuit of the IHS is configured for converting the high-power transmission to a voltage used by the IHS. When the power demand is not greater than the USB-PD power levels, the multimode adapter is configured for providing a USB-PD transmission. Some embodiments may detect events associated with high power demand and may preemptively configure the power circuit of the IHS for providing high-power outputs upon detecting such events.

Abstract: Power monitor information in an information handling system may be adjusted based on a battery voltage to account for a battery discharge state. The power monitor information may be scaled higher when the battery voltage is low to encourage the system to throttle and decrease power consumption. This adjustment increases the likelihood that the battery remains within safe operating limits.

Abstract: A method of operating a memory sub-system includes receiving an input voltage at a power management (PM) component of a memory sub-system, where the PM component includes a capacitive voltage divider (CVD), a linear voltage regulator (LVR), and a switching voltage regulator (SVR). The method includes determining whether the input voltage corresponds to a low power mode of the memory sub-system and that the input voltage is higher than an uppermost supply voltage at which a memory component of the memory sub-system is configured to operate. The method further includes selectably coupling, responsive to a determination of the low power mode, the CVD and the LVR and sequentially reducing the input voltage by the CVD and the LVR to a supply voltage for the memory component, where the supply voltage is not higher than the uppermost supply voltage at which the memory component is configured to operate.

Abstract: A system and method of entering a low power mode includes an external tuner module having a first external tuner and a receiving device having a first receiving tuner. The receiving device has a controller determining an unused tuner from one of the first external tuner or first receiving tuner and controls entering a low power mode at the unused tuner.

Abstract: A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.

Abstract: Disclosed is an electronic apparatus comprising a memory which is electrically connected to a processor and in which at least one command associated with the execution of the processor is stored, wherein the command is configured such that information on the frequency of the woken-up state of a display for a designated period of time is collected upon execution of the processor and that the information on the frequency of the woken-up state is compared with designated conditions, and a sensitivity associated with the detection of the arrangement status of the electronic apparatus is adjusted or maintained according to whether the conditions are satisfied or not. Other various embodiments as understood from the specification are possible.

Abstract: In one embodiment, a network of SSDs includes a switch with a plurality of powered ports configured to be communicatively coupled to a controller and a host client and a plurality of SSDs configured to be communicatively coupled to the plurality of powered ports. The switch is configured to deliver up to a predefined power level to each of the plurality of SSDs via the plurality of powered port. Each of the plurality of SSDs consumes power. The controller is configured to manage the predefined power level for each of the plurality of SSDs by identifying the power consumed by each of the plurality of SSDs and allocating a new power level to each of the plurality of SSDs based on the power consumed by each of the plurality of SSD. In one embodiment, the switch and the plurality of SSDs are configured to occupy a server rack space.

Abstract: An electronic device for controlling voltage and a method therefor are provided. The electronic device includes a power regulator, a connector including one or more signal terminals and one or more power terminals electrically connected to the power regulator, and a control circuit electrically connected to the one or more signal terminals. The control circuit is configured to identify a type of an external electronic device connected through the connector, identify detected values for at least some of the one or more signal terminals based at least on the identified type corresponding to a predetermined type, and output, through the power regulator, a predetermined voltage to the external electronic device through the one or more power terminals based at least on the detected value being within a first predetermined range.

Abstract: Systems and methods employ an external energy storage device (e.g., intelligent battery pack) interposed between a an information handling system (IHS) and its AC-to-DC adapter. The information handling system may be a fixed compute system, may lack an internal battery and/or may execute an operating system that does not have power management capability. The external energy storage device provides power and power state information to the IHS, e.g., that is based on state of charge (SOC) of the battery and/or absence/presence of AC power. IHS may perform one or more actions based on the power state information such as automatically save data and shutdown when notified AC power is lost and/or SOC is low, and may automatically restart and restore saved data when notified AC power is restored and/or SOC is sufficiently high. The external energy storage device may actively signal or command the IHS to act or may passively supply power state information and let the IHS decide how to act.

Abstract: A security code module is provided that a developer may include in an application. The application, when downloaded onto a mobile communications device, includes the security code module. The security code module then initiates a request to a server to determine the status of the mobile communications device. When the status indicates that the mobile communications device is not in the possession of the registered owner, a security component on the server performs an action in response.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes: may determine a first amount of power consumed by a processor of an information handling system; may configure power consumed by the processor to a second amount of power, lower than the first amount of power; may determine a first performance value based at least on a first change of frames per second and a first change of temperature; may determine a second performance value based at least on a second change of frames per second and a second change of temperature; may determine that the second performance value is greater than the first performance value; may configure power consumed by the processor to the second amount of power; and may configure power consumed by the a graphics processing unit of the information handling system to a third amount of power.

Abstract: The present application provides a method, a processing unit (12), a touch control chip (11), a device, and a medium for processing a configuration file. The method includes: determining (S201) the configuration file of a touch control chip (11); and writing (S202) the configuration file to the touch control chip (11); where the configuration file comprises a plurality of first configuration modules which are respectively used for configuring parameters with different attributes for the touch control chip (11). Thus, the configuration efficiency of the touch control chip (11) is improved.

Abstract: A periodic process performing system includes a system processor to which a first periodic real-time process, which starts to be executed starts for each of a first time interval from a first start time, is assigned; a wakeup logic which provides the system processor with a first state capable of executing the first periodic real-time process; and a counter which supplies a first tick signal to the wakeup logic for each of the first time interval from a second start time earlier than the first start time, and supplies a second tick signal to the system processor for each of the first time interval from a third start time between the first start time and the second start time.

Abstract: An operation parameter configuration method includes configuring at least two groups of operation parameters of an application, detecting a startup signal of the application in real time, confirming one of the at least two groups of operation parameters according to the startup signal, and starting the application in a foreground of the electronic device according to one confirmed group of operation parameters. The at least two groups of operation parameters include a group of default operation parameters and a group of optimal operation parameters. The group of optimal operation parameters are calculated according to a history of execution of the application by an electronic device. The group of optimal operation parameters is calculated according to a history of execution of the application in the foreground of the electronic device.

Abstract: An information handling system may reset components logged in a memory of the information handling system. For example, an information handling system may determine components logged in an information handling system memory and may perform a bulk reset of the logged components.

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Abstract: It is disclosed an electronic device to control temperature and computing performance of at least one processing unit. An event generation module is configured to receive an internal temperature signal representative of the internal temperature of the processing unit and to generate an event signal indicating the need to recalculate the value of at least one control signal controlling the computing performance of the processing unit and its dissipated thermal power. An event management module is configured to receive the event signal, calculate a control action for controlling the computing performance of the processing unit and the dissipated thermal power thereof, and generate a first candidate driving signal carrying said control action. An operating module is configured to receive the first candidate driving signal and to generate the at least one control signal as a function of the first candidate driving signal.

Abstract: Systems, methods, and computer-readable storage media are provided for parallel initiating of devices in a system. The method includes generating an affinity table that stores option ROM execution data including first data associated with a first device and second data associated with a second device and triggering, based on the affinity table, a first initialization of the first device and executing a first option ROM code during a pre-boot phase and triggering, based on the affinity table, a second initialization of the second device and executing a second option ROM code during the pre-boot phase. Triggering the first initialization of the first device and triggering the second initialization of the second device during the pre-boot phase is performed such that at least a part of the first initialization of the first device and at least part of the second initialization of the second device are executed in parallel.