Abstract: A system and method of entering a low power mode includes an external tuner module having a first external tuner and a receiving device having a first receiving tuner. The receiving device has a controller determining an unused tuner from one of the first external tuner or first receiving tuner and controls entering a low power mode at the unused tuner.

Abstract: A bootable update image file may be configured to, if operating system driver updates associated with a firmware update are boot-critical: modify a boot order of the information handling system to cause the information handling system to boot to an operating system of the information handling system such that the operating system fetches driver update packages from an update partition of the information handling system, applies the driver update packages, and modifies the boot order to cause the information handling system to boot to the bootable image file in a subsequent boot and in the subsequent boot, apply the firmware update; and, if driver updates are non-boot-critical: apply the firmware update and modify the boot order to cause the information handling system to boot to the operating system such that the operating system fetches the driver update packages from an update partition and applies the driver update packages.

Abstract: An external device and an information handling system may be attached through a single port connection to provide bi-directional transfer or data and power through the port connection. The port connector may allow the information handling system to function as both a power source and a power sink. This allows the information handling system to provide power to certain external devices from an internal battery to avoid data corruption when power to an external device is unexpectedly lost. When AC power is restored to the external device, the information handling system may be reconfigured to not transmit power to the external device and to receive power from the external device to operate the information handling system.

Abstract: A method may include assigning a core identifier of an active core to an idle core. After synchronizing the active core and idle core, the active core is inactivated.

Abstract: An apparatus is described herein. The apparatus includes a secure enclave, and the secure enclave comprises a scanning mechanism and a reboot mechanism. The apparatus also includes a negotiation module, wherein the negotiation module is to negotiate a packet type and a payload for a reboot packet and in response to the scanning mechanism detecting the reboot packet the reboot mechanism is to reboot a computing device.

Abstract: According to the invention, a method for determining what hardware components are installed on a computing device is disclosed. The method may include identifying the computing device, and determining, based on the computing device, a hardware component of the computing device. The method may also include retrieving information about the hardware component, and setting, based at least in part on the information about the hardware component, a parameter for an algorithm of software on the computing device.

Abstract: An electronic apparatus includes a main CPU, a main power supply control unit which conducts power supply to the main CPU and conducts supply control of the power, a sub power supply control unit which conducts power supply to the main power supply control unit, and a first switch which switches on and off power supply from the sub power supply control unit to the main power supply control unit.

Abstract: A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.

Abstract: A computing device has an energy storage device system with one or more energy storage devices. A target run-time is obtained, which refers to how long the computing device is to run given the current amount of energy in the energy storage device(s). A predicted power usage over the target run-time is determined, and what, if any, power management actions to take in order to achieve the target run-time are determined. The power management actions are then taken. A target charge-time is also obtained, which refers to how long the computing device is to take to charge the energy storage device(s) to a threshold level (e.g., 100% or fully charged). A predicted power gain over the target charge-time is determined, and what, if any, power management actions to take in order to achieve the target charge-time are determined. The power management actions are then taken.

Abstract: When an electronic apparatus including a core chip and a hub controller chip is connected to an apparatus on the host side, a USB hub controller in the hub controller chip executes a process on a configuration between the USB hub controller and the apparatus on the host side and sets a limit value of power to be supplied, from a first limit value to a second limit value higher than the first limit value, and a VBUS current controller in the hub controller chip supplies the core chip with a power supply voltage generated based on a supplied power, which allows to maintain a configuration state between the apparatus on the host side and the USB hub controller at a time of starting up or at a time of class switching of the core chip and supply the core chip with the sufficient power.

Abstract: An apparatus is provided comprising a system including one or more electronic components; a power input unit arranged to supply power to the system; and a power management module configured to: detect whether the system is in an abnormal state, and in response to detecting that the system is in the abnormal state, adjust at least one of (i) power supplied from a battery to the system, (ii) the power supplied from the power input unit to the system, and (iii) power supplied from the power input unit to the battery.

Abstract: A cycle control circuit may include a judgement pulse generation circuit, a detection signal generation circuit or a flag generation circuit. The judgement pulse generation circuit may be configured to set a predetermined value based on an initialization signal and a period signal, and to generate a judgment pulse. The detection signal generation circuit may be configured to generate a detection signal from a reference flag. The flag generation circuit may be configured to generate a reference flag based on a reference signal. A cycle of the reference signal may be maintained or adjusted based on the reference flag.

Abstract: Examples include techniques for booting a computing system. A processor semiconductor chip includes one or more processing cores and an embedded non-volatile random-access memory (NVRAM), the NVRAM storing instructions that when executed by the one or more processing cores manages a boot process for a computing system.

Abstract: Example implementations relate to a parallel backup power supply. For example, a parallel backup power supply system can include a plurality of backup power supply cells that support a plurality of loads. Each of the backup power supply cells can include a charging module to charge an associated backup power supply cell among the plurality of backup power supply cells and a cell controller. The cell controller is to can be configured to control the charging module and communicate with a management module. The parallel backup power supply system can also include the management module to activate each of the plurality of backup power supply cells to provide backup power in parallel to the plurality of loads as each of the plurality of backup power supply cells is fully charged.

Abstract: A data management circuit is provided. The data management circuit includes a volatile memory, a power supply circuit, and a signal receiving circuit. An output terminal of the power supply circuit is coupled to the volatile memory, and an output terminal of the signal receiving circuit is coupled to the output terminal of the power supply circuit and the volatile memory. The power supply circuit is configured to provide power to the volatile memory. The signal receiving circuit is configured to receive a wireless control signal and to output a data clearance signal corresponding to the wireless control signal, such that data recorded in the volatile memory is cleared by the data clearance signal.

Abstract: Techniques provide for persistently storing state information regarding configuration requirements, such as STIG (Security Technical Implementation Guides) requirements. The state information may indicate whether all or one or more selected categories of requirements are enabled. The state information may be persistently stored and applied or hardened across multiple processor nodes as well as across system upgrades.

Abstract: Aspects of the disclosure include an apparatus that has a first clock generator and a second clock generator. The first clock generator is configured to drive a first circuit, causing the first circuit to (i) receive a signal corresponding to an audio input, and (ii) determine whether an energy level of the signal exceeds a predetermined threshold. The second clock generator is activated when the first circuit determines that the energy level of the signal exceeds the predetermined threshold. The second clock generator is configured to drive a second circuit, causing the second circuit to determine whether the signal matches a predetermined pattern. A third circuit is activated when the second circuit determines that the signal matches the predetermined pattern.

Abstract: An electronic device is provided. The electronic device includes a first memory, a second memory, and a controller. The first memory stores data of a boot-up instruction, and the second memory stores setting information associated with a condition in which communication with an external device is performed. The controller stores the setting information having a self-setting value in the second memory, before the second memory stores the setting information based on a command from the external device. The controller provides the data of the boot-up instruction to the external device in response to a memory read request received from the external device under a condition defined by the self-setting value.

Abstract: A bridge module is provided. The bridge module comprise a first transmission unit electrically connected to a host to receive a power status signal from the host; a second transmission unit electrically connected to a data transceiver device to have data transmission with the data transceiver device at a download data transmission speed; and a processing device electrically connected to the first transmission unit and the second transmission unit, and configured to adjust the download data transmission speed and a processor clock of the processing device according to the power status signal. An operation method is also provided.

Abstract: A power storage adapter (PSA) may be connected to multiple battery-powered devices. A PSA controller may be configured to receive respective requests to supply electrical power to a first device and a second device, to determine that the power storage adapter does not have sufficient power supply capacity to satisfy both requests, to determine that a respective state of charge (SOC) of at least one device battery is below a first battery SOC threshold, and to prioritize supplying electrical power to a selected one of the devices at the expense of the other device based on a battery charging prioritization policy. The selected device may be prioritized until the battery SOC exceeds a battery SOC threshold or for a predetermined time period. The battery charging prioritization policy may specify relative charging priorities for the device batteries and a PSA battery dependent on whether AC line power is available.