Abstract: A level count disparity is determined based at least in part on an expected count of a plurality of cells in a solid state storage and an observed count of the plurality of cells in the solid state storage, where the observed count is obtained from a read performed on the solid state storage using a previous read threshold. A next read threshold is determined based at least in part on the level count disparity. A read is performed on the solid state storage using the next read threshold to obtain read data and error correction decoding is performed on the read data.

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

Abstract: A control method of a programming process for a three-dimensional (3D) NAND flash memory array comprises programming a bit-cell of the 3D NAND flash memory array in a programming stage; and verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage; wherein the programming stage comprises programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses; wherein the verification stage comprises reading the bit-cell of the 3D NAND flash memory array with lower or higher voltage than normal reading voltage pulse.

Abstract: Systems, apparatuses, and methods related to performing operations within a memory device are described. Such operations may be performed using data latched in multiple sense amplifiers that are distributed among a plurality of sense amplifiers of the memory device. For example, those sense amplifiers, among the plurality of sense amplifiers, storing data associated with the operation(s) can be determined, and the data can be selectively sent from the determined sense amplifiers to an operation unit, in which the operations are performed. The operations may be made without affecting a subsequent read command that requests data from the plurality of sense amplifiers.

Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.

Abstract: A ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element located between the gate electrode and the two-dimensional electron gas channel.

Abstract: A semiconductor device according to an embodiment includes first and second drain select transistors, first and second source select transistors, first and second memory cell transistors, third and fourth memory cell transistors, first and second bit lines, first to third select gate line, first and second word lines, and a controller. The controller is configured to execute, in the program loop, a program operation, a recovery operation and a verify operation in sequence. In the write operation of the first memory cell transistor, the controller is configured, at a first time of the recovery operation, to: apply a first voltage to the first select gate line; apply a second voltage to the third select gate line; and apply a third voltage to the first bit line.

Abstract: An operating method of a non-volatile memory device including a plurality of memory cells respectively connected to a plurality of word lines is provided. The operating method includes applying an erase detect voltage to a selected word line of the plurality of word lines to perform an erase detect operation on memory cells connected to the selected word line in response to a program command, applying a program voltage to the selected word line after the erase detect operation, and counting a number of undererased cells of the memory cells on which the erase detect operation has been performed.

Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

Abstract: A method for programming a memory device and a memory system are provided, wherein the method for programming the memory device includes steps below. First, a program command is proposed. Second, a width of a pulse about to provide to strings of memory cells of the memory device is determined according to a temperature data of the memory device. Then, the pulse is provided to the strings of memory cells to start doing a program operation. The width of the pulse becomes narrower as a temperature of the memory device is raised.

Abstract: Methods, systems, and devices for performing quick precharge command sequences are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received precharge command using a first set of operations having a first duration—rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received precharge command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations.

Abstract: Provided are an apparatus, memory device, and method for using variable voltages to discharge electrons from a memory array during verify recovery operations. In response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, a memory controller concurrently applies voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons and applies voltages to the bitlines to perform bitline stabilization.

Abstract: A memory device includes a plurality of planes, a row driver and a controller. A method of programming the memory device includes in a program operation, the row driver applying a program pulse to a plurality of memory cells of a first plane of the plurality of planes; after the row driver applies the program pulse to the plurality of memory cells, the controller verifying if the plurality of memory cells have reached a predetermined program state; and if a preset number of the plurality of memory cells have failed to reach the predetermined program state after the plurality of memory cells have been verified for a predetermined number of times, the controller disabling the first plane.

Abstract: A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.

Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.

Abstract: The present technology relates to a memory device and method of operating the memory device. The memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit performs a plurality of program loops each including a program operation and a verify operation on selected memory cells of the plurality of memory cells. The control logic controls the peripheral circuit to increase a potential of selected bit lines.

Abstract: The present disclosure relates to method of operating a memory device, the memory device includes a memory cell array, a voltage generator, and control logic. The voltage generator configured to increase a power supply voltage. The control logic is configured to store a time based on the increased power supply voltage and a reference voltage. The reference voltage is a voltage level used to perform an operation on the memory cell array.

Abstract: A method is presented for forming an on-chip security key. The method includes electrically connecting a pair of phase change memory (PCM) elements in series, electrically connecting a programming transistor to the pair of PCM elements, electrically connecting an input of an inverter to a common node of the pair of PCM elements, setting the PCM elements to a low resistance state (LRS) in an initialization stage, applying a RESET pulse to generate a security bit and to cause one of the PCM elements to change to a high resistance state (HRS), and generating a logic “1” or “0” at the output of the inverter.

Abstract: A nonvolatile memory device including: a memory cell array, the memory cell array including a plurality of cell strings, at least one of the cell strings including a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate, at least one of the memory cells is a multi-level cell storing at least three bits; and a control logic circuit configured to control a page buffer to read a fast read page of the memory cells with one read voltage and at least two normal read pages of the memory cells with the same number of read voltages.

Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.