Patents Examined by Gene N. Auduong
  • Patent number: 11031779
    Abstract: A memory system includes a non-volatile memory block, a random bit block, and a sense amplifier. The non-volatile memory block includes a plurality of non-volatile memory cells for storing a plurality of bits of data. Each of the non-volatile memory cells includes a first storage transistor. The random bit block includes a plurality of random bit cells for providing a plurality of random bits. Each of the random bit cells includes a second storage transistor and a third storage transistor. The sense amplifier senses a first read current of a non-volatile memory cell during a read operation of the non-volatile memory cell and senses a second read current of a random bit cell during a read operation of the random bit cell. The first storage transistor, the second storage transistor, and the third storage transistor are storage transistors of the same type.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 8, 2021
    Assignee: eMemory Technology Inc.
    Inventor: Wein-Town Sun
  • Patent number: 11031400
    Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 11017825
    Abstract: A memory circuit includes: memory cells each including a storage transistor having a first configuration; and a tracking circuit including: a tracking bit line having first and second intermediary nodes; a tracking word line; a first finger circuit (coupled between the first intermediary node and a reference voltage node) including: a first set of first tracking cells, each including a first shadow transistor having the first configuration; and a second finger circuit (coupled between the second intermediary node and the reference voltage node) including: a second set of second tracking cells, each including a second shadow transistor having the first configuration; gate terminals of the first and second shadow transistors being coupled with the tracking word line; and a switch configured to selectively couple the first intermediary node with the second intermediary node and thereby selectively couple the first and second finger circuits in parallel.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuoyuan (Peter) Hsu, Jacklyn Chang
  • Patent number: 11017849
    Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: May 25, 2021
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
  • Patent number: 11011235
    Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: May 18, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasushi Nagadomi
  • Patent number: 11011577
    Abstract: An One-Time Programmable (OTP) memory is built in at least one of nano-wire structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one nano-wires. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one nano-wires can be built on an isolated structure that has at least one MOS gate dividing nano-wires into at least one first active region and a second active region. The first active region can be doped with a first type of dopant and the second active region can be doped with a first or second type of dopant. The OTP element can be coupled to the first active region with the other end coupled to a first supply voltage line. The second active region can be coupled to a second voltage supply line and the MOS gate is coupled to a third voltage supply line.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: May 18, 2021
    Assignee: Attopsemi Technology Co., Ltd
    Inventor: Shine C. Chung
  • Patent number: 11004479
    Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 11, 2021
    Assignee: Arm Limited
    Inventors: Mudit Bhargava, Shidhartha Das, George McNeil Lattimore, Brian Tracy Cline
  • Patent number: 11004520
    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 11, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
  • Patent number: 11004493
    Abstract: Methods, systems, and devices for differential amplifier schemes for non-switching state compensation are described. During a read operation, a first node of a memory cell may be coupled with an input of differential amplifier while a second node of the memory cell may be biased with a first voltage (e.g., to apply a first read voltage across the memory cell). The second node of the memory cell may subsequently be biased with a second voltage (e.g., to apply a second read voltage across the memory cell), which may support the differential amplifier operating in a manner that compensates for a non-switching state of the memory cell. By compensating for a non-switching state of a memory cell during read operations, read margins may be increased.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Vimercati, Xinwei Guo
  • Patent number: 11004485
    Abstract: A memory system includes: a plurality of memory dies, and a controller selects a second read request, including at least a portion of a plurality of first read requests, so that the memory dies interleave and output data corresponding to the first read requests, and performs a correlation operation for the selected second read request, when the second read request is selected, the controller determines whether the correlation operation is performed or not before a time at which the second read request is selected, determines whether the correlation operation is successful or not, determines a pending credit in response to an operation state of the memory dies at the time at which the second read request is selected, and determines whether to perform the correlation operation or not for the second read request that is selected at the time at which the second read request is selected based on the pending credit.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 10998050
    Abstract: Discussed herein are systems and methods for protecting against transistor degradation in a high-voltage (HV) shifter to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises memory cells and a HV shifter circuit that includes a signal transfer circuit, and first and second HV control circuits. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The first HV control circuit couples a bias voltage to the P-channel transistor for a first time period, and the second HV control circuit couples a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to reduce degradation of the P-channel transistor. The transferred high voltage can be used to charge the access line to selectively read, program, or erase memory cells.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Patent number: 10998066
    Abstract: Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Sebastien Andre Jean
  • Patent number: 10991433
    Abstract: A memory device having non-volatile memory cells and a controller. In response to a first command for erasing and programming a first group of the memory cells, the controller determines the first group can be programmed within substantially 10 seconds of their erasure, erases the first group, and programs the first group within substantially 10 seconds of their erasure. In response to a second command for erasing and programming a second group of the memory cells, the controller determines that the second group cannot be programmed within substantially 10 seconds of their erasure, divides the second group into subgroups of the memory cells each of which can be programmed within substantially 10 seconds of their erasure, and for each of the subgroups, erase the subgroup and program the subgroup within substantially 10 seconds of their erasure.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: April 27, 2021
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Viktor Markov, Alexander Kotov
  • Patent number: 10991440
    Abstract: Data from a first portion of a memory cell of a plurality of memory cells is read. A first programming pass is performed on another memory cell of the plurality of memory cells by providing new data to the another memory cell. A second programming pass is performed on the memory cell by providing additional data to the first portion of the memory cell based on the reading of the first portion of the memory cell. The first programming pass and the second programming pass correspond to a two-pass programming operation associated with the plurality of memory cells.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yang Zhang
  • Patent number: 10990119
    Abstract: A reference voltage generation circuit of the invention includes: PMOS transistors P1 and P2 configured to provide current sources with same current to a first current path and a second current path; a bipolar transistor Q1 connected to the PMOS transistors P1 on the first current path; a bipolar transistor Q2 connected to the PMOS transistors P2 on the second current path; a differential amplifier AMP controlling the gates of the PMOS transistors P1 and P2, such that a voltage of a node VN and a voltage of a node VP are equal; an output node BGR outputting a reference voltage Vref; and a reference voltage guarantee portion 130 outputting a detecting signal BGRDET when a differences between the voltage of the node VN and the voltage of the node VP is maintained below a determined value.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 27, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Hiroki Murakami
  • Patent number: 10985758
    Abstract: A random code generator includes a memory cell, two write buffers and two sensing circuits. The memory cell includes a first program path between a first source line and a first bit line, a second program path between the first source line and a second bit line, a first read path between a second source line and a third bit line, and a second read path between a third source line and a fourth bit line. The two write buffers are connected with the first bit line and the second bit line, respectively. The two sensing circuits are connected with the third bit line and the fourth bit line, respectively. The two sensing circuits generate a first output signal and the second output signal to the corresponding write buffers according to the read currents in the corresponding read paths.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: April 20, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Wei-Ming Ku, Wein-Town Sun, Ying-Je Chen
  • Patent number: 10978157
    Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: April 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masanobu Shirakawa, Kenta Yasufuku, Akira Yamaga
  • Patent number: 10964392
    Abstract: A memory system includes a controller suitable for providing first data, a cache program command corresponding to the first data, second data, and a normal program command corresponding to the second data; and a memory device suitable for programming the first data to a target die according to the cache program command, setting the target die to a normal state after the program operation for the first data is completed, and programming the second data to the target die according to the normal program command.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 30, 2021
    Assignee: SK hynix Inc.
    Inventor: Joo-Young Lee
  • Patent number: 10964468
    Abstract: A magnetic memory structure employs electric-field controlled interlayer exchange coupling between a free magnetic layer and a fixed magnetic layer to switch a magnetization direction. The magnetic layers are separated by a spacer layer disposed between two oxide layers. The spacer layer exhibits a large IEC while the oxide layers provide tunnel barriers, forming a quantum-well between the magnetic layers with discrete energy states above the equilibrium Fermi level. When an electric field is applied across the structure, the tunnel barriers become transparent at discrete energy states via a resonant tunneling phenomenon. The wave functions of the two magnets then can interact and interfere to provide a sizable IEC. IEC can control the magnetization direction of the free magnetic layer relative to the magnetization direction of the fixed magnetic layer depending on the sign of the IEC, induced by a magnitude of the applied electric field above a threshold value.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: March 30, 2021
    Assignee: The Regents of the University of California
    Inventors: Sayeef Salahuddin, Shehrin Sayed
  • Patent number: 10957394
    Abstract: Apparatuses and techniques are described for pre-charging NAND string channels in a pre-charge phase of a program operation. In one aspect, a hole-type pre-charge process is used at the source end of a NAND string, where a bottom of the NAND string is connected to a p-well of a substrate. By applying a positive voltage to the p-well and a lower voltage, such as 0 V or a negative voltage, to the source-side select gate transistors and the memory cells, the holes from the p-well are injected into the channel In another approach, the hole-type pre-charge process and an electron-type pre-charge process are used sequentially in separate time periods. In another approach, the hole-type pre-charge process is used at the source end of a NAND string while the electron-type pre-charge process is used at the drain end of the NAND string.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: March 23, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Han-Ping Chen, Wei Zhao, Henry Chin