Abstract: One controller for controlling operation of a memory device includes an output circuit configured to supply a chip select signal, an address signal, a command signal, and a clock signal to the memory device, and a data processing circuit configured to process read data and write data through a data terminal based on the chip select signal, the address signal, the command signal, and the clock signal supplied by the output circuit. The controller is configured to supply the address signal and the command signal to the memory device a predetermined duration after the output circuit supplies the chip select signal.

Abstract: A memory circuit including: memory cells, each including a storage cell transistor; a first tracking bit line; and a tracking circuit, electrically coupled between a first tracking word line and a reference voltage node, including a first set of first tracking cells, each first tracking cell including a first cell transistor having a same transistor configuration as each storage cell transistor; and wherein: a driving capacity of the storage cell transistors of the memory cells has a storage cell statistical distribution that exhibits a weak bit current value; a driving capacity of the first cell transistors of the first set of tracking cells has a first tracking cell statistical distribution that exhibits a first strong bit current value; and a first quantity of the first tracking cells is sufficient to cause the first strong bit current value to be equal to or less than the weak bit current value.

Abstract: A method for estimating precipitation values and associated uncertainties is provided. In an embodiment, precipitation records that indicate the occurrence and intensity of precipitation at specific locations are received by a weather computing system. The weather computing system uses the gauge information to separately create multiple realizations of precipitation occurrence fields and precipitation intensity fields. The weather computing system may model the occurrence of precipitation by proposing a value for each point independently and using the proposed value to update all prior proposals. The weather computing system may model the intensity of precipitation by modeling the spatial correlation of precipitation intensity and sampling from distributions at each location to determine the intensity of precipitation at each location. The weather computing system may then combine the precipitation intensity and occurrence fields into one or more final estimate fields.

Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

Abstract: Memory cells with improved tunneling magnetoresistance ratio (TMR) are disclosed. In some embodiments such devices may include a magnetoresistive tunnel junction (MTJ) element coupled in series with a tunneling magnetoresistance enhancement element (TMRE). The MTJ element and TMRE may each be configured to transition between high and low resistance states, e.g., in response to a voltage. In some embodiments, the MTJ and TMRE are configure such that when a read voltage is applied to the cell while the MTJ is in its low resistance state the TMRE is driven to is low resistance state, and when such voltage is applied while the MTJ is in its high resistance state, the TMRE remains in its high resistance state. Devices and systems including such memory cells are also disclosed.

Abstract: According to one embodiment, a semiconductor storage device includes: a first conductor coupled to a first end of a first cell; a second conductor which couples between a second end of the first cell and a first end of a second cell; a third conductor coupled to a second end of the second cell; a first current source being capable of coupling to the first cell via the first conductor; a second current source being capable of coupling to the second cell via the third conductor; a first sense amplifier configured to read data from the first cell based on a current flowing from the first current source to the first cell; and a second sense amplifier configured to read data from the second cell based on a current flowing from the second cell to the second current source.

Abstract: A memory device and an operating method thereof are provided. A memory device may include a plurality of source lines coupled to a memory block. The memory device may include a plurality of strings coupled to each of the source lines. The memory device may include a row decoder configured to selectively transmit voltages to local lines corresponding to a selected source line among the source lines.

Abstract: An apparatus and method for estimating state information of a battery are provided. The apparatus may estimate the state information from information, obtained by classifying and preprocessing battery information measured by a battery management system (BMS), using a pre-trained battery degradation model.

Abstract: A Magnetic Random Access Memory (MRAM) array has a plurality of main MRAM bitcells and a plurality of canary MRAM bitcells in which a first Magnetic Tunnel Junction (MTJ) diameter of each of the main MRAM bitcells is larger than any second MTJ diameter of any of the canary bitcells. Test circuitry is configured to periodically poll the canary bitcells to determine if values stored at the canary bitcells match expected canary values. When the values do not match the expected canary values, the test circuitry is configured to indicate a presence of a magnetic field, and in response to determining the presence of the magnetic field, continue to poll the canary bitcells until the values match the expected canary values which indicates the magnetic field is no longer present.

Abstract: According to one embodiment, a semiconductor memory device includes, a memory cell array, a first clock signal line, a second clock signal line to which first and second input/output buffer circuits are coupled in the order from one end toward the other end, a first buffer coupled to the one end of the second clock signal line, and a second buffer coupled to the other end of the second clock signal line. When a write operation is performed, a clock signal is input to the first and second input/output buffer circuits through the first buffer, and when a read operation is performed, a clock signal is input to the first and second input/output buffer circuits through the second buffer.

Abstract: A method of operating a nonvolatile memory device is provided. The nonvolatile memory device includes a memory cell array including a plurality of memory cells. The method includes: the nonvolatile memory device determining an operation mode based on the received command, the nonvolatile memory device generating a comparison voltage based on the determined operation mode, the nonvolatile memory device comparing the comparison voltage with a reference voltage to generate a result, and the nonvolatile memory device performing a recovery operation on at least one of the memory cells depending on the result.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells coupled between a common source line and a bit line, and a voltage generator applying operating voltages to word lines coupled to the memory cells or discharging potential levels of the word lines, wherein during a program verify operation, the voltage generator applies a program verify voltage and a pass voltage as the operating voltages to the word lines, and subsequently applies a set voltage to the common source line during a period in which the memory cells are turned on.

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.

Abstract: A profiling-based energy-aware recommendation method for a cloud platform at a cloud mediator interface may include: collecting usage data of a cloud node over predetermined intervals of time; generating and storing an energy usage profile for each node by using the collected usage data; acquiring real-time usage data from the cloud node; and comparing the real-time usage data with the generated energy usage profile so as to calculate a recommendation value.

Abstract: A system and method for determining kerogen porosity of a formation for downhole operations is described herein. The method includes calculating a first formation characteristic and a second formation characteristic at a processor of an information handling system. The method further includes determining a kerogen porosity of the formation based, at least in part, on the first formation characteristic and the second formation characteristic. And the method also includes performing a downhole operation based, at least in part, on the determined kerogen porosity.

Abstract: Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of the memory cell prior to applying a second voltage to the memory cell. The second voltage may be applied to facilitate a sensing operation once the selection component is activated. The first voltage may be applied during a first portion of an access operation and may be used in determining a threshold voltage of the selection component. The subsequently applied second voltage may be applied during a second portion of the access operation and may have a magnitude associated with a preferred voltage for accessing a ferroelectric capacitor of the memory cell. In some cases, the second voltage has a greater rate of increase over time (e.g., a greater “ramp”) than the first voltage.

Abstract: A voltage regulator includes a first feedback loop and a second feedback loop. The first feedback loop includes a charge pump outputting a first output voltage, a first transistor ladder and a control circuit. The first transistor ladder divides the first output voltage to generate a first feedback voltage. The control circuit receives the first feedback voltage and controls a level of the first output voltage according to the first feedback voltage and a reference voltage. The second feedback loop includes a power transistor, a second transistor ladder and an operational amplifier. The power transistor receives the first output voltage to output a second output voltage. The second transistor ladder divides the second output voltage to generate a second feedback voltage. The operational amplifier outputs a control signal to the power transistor by receiving the second feedback voltage and a reference voltage selected from one of a plurality of levels.

Abstract: Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.