Abstract: An example apparatus includes a memory device having first sensing circuitry positioned adjacent an edge of an edge array section and selectably coupled to a row memory cells, the first sensing circuitry including a first sense amplifier selectably coupled via a first sense line to a first memory cell in the row and via a second sense line to the first memory cell. The example apparatus includes second sensing circuitry positioned at an opposite edge of the edge array section and selectably coupled to the row via a third sense line, the second sensing circuitry including a second sense amplifier selectably coupled via the third sense line to a second memory cell in the row. The example apparatus further includes a component positioned outside the edge array section and proximate the first sensing circuitry, the component configured to perform an operation based on data sensed by the first sensing circuitry.

Abstract: A semiconductor memory device includes a memory cell array coupled to a plurality of word lines, a voltage generator generating a program voltage and first and second pass voltages in response to voltage generation control signals, an address decoder selectively applying the program voltage and the first and second pass voltages to the plurality of word lines in response to address decoder control signals, and a control logic controlling the voltage generator and the address decoder to perform a program operation.

Abstract: A battery capacity estimating apparatus and a battery capacity estimating method of the battery capacity detecting apparatus are provided. A state of charge and a state of health of a battery are calculated according to dynamic impedance of the battery.

Abstract: Provided is a sense amplifier circuit for detecting data having been read from a memory cell. The sense amplifier circuit includes: a potential control unit for controlling the potential of a bit line connected to a memory cell; a current amplifier unit for amplifying a readout current flowing from the memory cell to the bit line so as to produce an amplified current; and a detection unit for detecting data having been read from the memory cell on the basis of the amplified current. The potential control unit controls the potential of the bit line in a data readout duration, and the data readout duration includes a current amplification duration, and the current amplifier unit amplifies the readout current in the current amplification duration.

Abstract: A memory system may include: a memory device including a plurality of memory blocks configured in a plurality of super memory blocks; and a controller suitable for detecting two or more bad super memory blocks each including at least one bad block among the super memory blocks, selecting at least one victim super memory block among the bad super memory blocks, and replacing the at least one bad block in each remaining bad super memory block with at least one normal block of the victim super memory block.

Abstract: A programmable logic controller comprises a processor, a PLC operating environment, a device memory, and an app container. The PLC operating environment is configured to execute a controller automation program providing a plurality of skill functions. The device memory comprises a plurality of apps which are configured to perform a discrete set of automation functions using the plurality of skill functions. The app container is logically separate from the PLC operating environment and configured to provide a runtime environment for the apps.

Abstract: Disclosed are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory blocks sharing one or more drain select lines; a peripheral circuit configured to perform a program operation on the memory cell array; and a control logic configured to control the peripheral circuit to coding-program one or more drain select transistors included in each of the plurality of memory blocks.

Abstract: An apparatus comprises receiving a user prompt in a blood glucose (BG) management device to start a determination of an effective correction factor, receiving sampled blood glucose data of a patient obtained during a specified time duration, including a time duration after delivery of an initial insulin correction bolus, determining the effective correction factor using the BG management device according to a determined decrease in the blood glucose level of the patient and an amount of insulin in the initial insulin correction bolus, and cancelling the determination of the effective correction factor if a blood glucose level of the patient is outside of a specified range of blood glucose levels.

Abstract: The rechargeable battery parameter estimation apparatus includes: a current measurement part for measuring a current flowing through a rechargeable battery, the current measurements having an offset error; a first coefficient calculation part for calculating a first coefficient, which is a partial derivative of an estimated value of an state of charge (SoC) of the battery with respect to the offset error; a second coefficient calculation part for calculating a second coefficient, which is a partial derivative of the estimated value of the SoC with respect to a capacity error, which is a difference of a typical full charge capacity from an actual full charge capacity of the battery; and an error estimation part for estimating the offset error and the capacity error from derivative information including the first coefficient and the second coefficient, the current flowing through the battery, and the estimated value of the SoC.

Abstract: A method and system for determining a speed of a vehicle based on a GPS speed captured from a Global Positioning System (GPS). A capturing module captures GPS speed Vx and a horizontal accuracy value corresponding to a time stamp Tx. A speed modification module modifies the GPS speed Vx corresponding to the time stamp Tx. A speed correcting module corrects the GPS speed Vx corresponding to the time stamp Tx. The GPS speed may be corrected by filtering an error in the GPS speed by using a Slope dependent averaging (SDA) filter in order to obtain a first corrected speed Vx?. Further, the first corrected speed is corrected by selecting one of a center weight (CW) filter and an edge weight (EW) filter, based upon a pre-defined condition, in order to obtain a second corrected speed Vx? indicating the speed of the vehicle.

Abstract: A system and method for learning and asserting what portions of a utility GIS network model are incorrect or flawed as they relate to real world conditions, and what the correct real world relationships are in the field is described. The system and method leverage available smart grid data to assess the quality of a primary (GIS) source data set; quality data renders derived analyzes across the utility valid, sound, and action worthy. The system and method utilize existing partially correct electrical network distribution model data and various non-specialized source data including smart meter, spatial, and customer information data collected from the network to test, validate and suggest corrections to the connectivity model. By forming putative ground truth assignments between utility components, the system tests the assumptions by examining the geospatial proximity and correlating voltage and event data over time to form refined hypothesis.

Abstract: Various embodiments of the present technology provide methods for calibrating a full-charge capacity of a battery system. In some implementations, the battery system can be caused to enter into a static learning mode. During the static learning mode, current and past battery cell characteristics for each battery cell of the battery system can be collected, analyzed, and used to build up or update a database of correlations between a full-charge capacity of a specific type of battery cell and cell characteristics of a corresponding type of battery cell. The full-charge capacity of the battery system can be determined based at least upon cell characteristics of battery cells of the battery system, or the database of correlations between a full-charge capacity of a specific type of battery cell and cell characteristics of battery cells in the battery system.

Abstract: A signal processing system is provided and includes: a measurement apparatus that measures current and voltage which are supplied to a plurality of electric devices; and a processing apparatus that is connected to the measurement apparatus that estimates operation conditions of the respective electric devices. The measurement apparatus includes a detection unit that detects analog waveform data, a conversion unit that samples the analog waveform data and converts the sampled analog waveform data into digital waveform data, and a transmission unit that transmits the digital waveform data to the processing apparatus. The processing apparatus includes a reception unit that receives the digital waveform data, a storage unit that stores the digital waveform data, a separation unit that separates the stored digital waveform data into pieces, and an operation estimation unit that analyzes the pieces of digital waveform data and estimates the operation conditions.

Abstract: A method and apparatus for controlling an electronic device using a rotary control. The method includes receiving, by an electronic processor from an inductance sensor, a first inductance. The method further includes comparing, by the electronic processor, the first inductance to a first threshold. The method further includes, determining, by the electronic processor, a location for the rotary control when the first inductance exceeds the first threshold, the method further includes activating, by the electronic processor, a control function based on the location. The method further includes receiving, by the electronic processor from the inductance sensor, a second inductance. The method further includes determining, by the electronic processor, a delta based on the first inductance and the second inductance. The method further includes adjusting, by the electronic processor, the control function based on the delta.

Abstract: An apparatus includes a line-termination circuit and a continuous-time linear equalizer circuit. The line-termination circuit may be configured to generate a data signal in response to an input signal. The input signal generally resides in a first voltage domain. The input signal may be single-ended. The data signal may be generated in the first voltage domain. The continuous-time linear equalizer circuit may be configured to generate an intermediate signal by equalizing the data signal relative to a reference voltage. The continuous-time linear equalizer circuit generally operates in a second voltage domain. The first voltage domain may be higher than the second voltage domain.

Abstract: An operation method of a nonvolatile memory system includes receiving a write command from an external device, determining continuity of the write command based on an idle time, and performing a write operation of the write command in one of a fast mode and a normal mode based on the determination result.

Abstract: Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of the memory cell prior to applying a second voltage to the memory cell. The second voltage may be applied to facilitate a sensing operation once the selection component is activated. The first voltage may be applied during a first portion of an access operation and may be used in determining a threshold voltage of the selection component. The subsequently applied second voltage may be applied during a second portion of the access operation and may have a magnitude associated with a preferred voltage for accessing a ferroelectric capacitor of the memory cell. In some cases, the second voltage has a greater rate of increase over time (e.g., a greater “ramp”) than the first voltage.

Abstract: Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a ferroelectric memory element including a field effect transistor having a ferroelectric gate dielectric layer and a drain electrode. The nonvolatile memory device also includes a resistive memory element electrically connected in series to the drain electrode of the field effect transistor. A multilevel signal is stored in the nonvolatile memory device according to a channel resistance of the ferroelectric memory element and a resistance of the resistive memory element.

Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.

Abstract: A solid-state device configured to generate an electric signal indicative of a presence or an absence of a magnetic topological soliton is disclosed. The solid-state device includes a storage element configured to store a magnetic topological soliton. The storage element includes a topological insulator. The storage element also includes a magnetic strip arranged on the topological insulator. The solid-state device also includes a magnetic topological soliton detector configured to generate the electric signal indicative of the presence or the absence of the magnetic topological soliton in a detection region of the storage element. The magnetic topological soliton detector is adapted for detecting a spin-independent difference in tunneling amplitude, a difference in electrical resistance, or a difference in electrical conductivity through the topological insulator in the detection region due to the presence or the absence of the magnetic topological soliton in the detection region.