Patents Examined by George Fourson
  • Patent number: 10263023
    Abstract: A color filter layer and a light transmissive layer have a groove between a first color filter and a second color filter and between a first light transmissive portion and a second light transmissive portion. The groove contains a member located at least between the first color filter and the second color filter. The member has a refractive index higher than 1.0.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 16, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koichi Tazoe, Kazuya Igarashi
  • Patent number: 10263093
    Abstract: An optoelectronic semiconductor includes a carrier, a semiconductor main body having a first semiconductor layer, a second semiconductor layer, and a radiation emitting layer for generating electromagnetic radiation, the semiconductor main body having at least one recess extending through the radiation emitting layer; a first electrode and a second electrode; a first electrical connection layer electrically connected between the first semiconductor layer and the first electrode; a second electrical connection layer electrically connected between the second semiconductor layer and the second electrode and extending through the recess from the carrier to the second semiconductor layer; and a zener diode structure disposed between the first electrical connection layer and the second electrical connection layer so that the first electrical connection layer and the second electrical connection layer are electrically dependent, wherein at least a portion of the zener diode structure is located in a current path bet
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 16, 2019
    Assignee: HIGH POWER OPTO. INC.
    Inventors: Wei-Yu Yen, Li-Ping Chou, Wan-Jou Chen, Chih-Sung Chang
  • Patent number: 10256331
    Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a P+ layer (e.g., a substrate), an N? epi layer, a P-well, vertical insulated gates formed in the P-well, and N+ regions between at least some of the gates, so that vertical NPN and PNP transistors are formed. A source/emitter electrode is on top, and a drain/cathode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the source/emitter electrode. Some of the cells are passive, having gates that are either not connected to the active gates or having gates that are shorted to their associated N+ regions, to customize the input capacitance and lower the saturation current. Other techniques are described to form the passive cells.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: April 9, 2019
    Assignee: Pakal Technologies, Inc.
    Inventors: Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo, Vladimir Rodov
  • Patent number: 10249821
    Abstract: Design of side chains yielding highly amphiphilic conjugated polymers is proven to be an effective and general method to access lyotropic liquid crystalline mesophases, allowing greater control over crystalline morphology and improving transistor performance. The general strategy enables variations in structure and interactions that impact alignment and use of liquid crystalline alignment methods. Specifically, solvent-polymer interactions are harnessed to facilitate the formation of high quality polymer crystals in solution. Crystallinity developed in solution is then transferred to the solid state, and thin films of donor-acceptor copolymers cast from lyotropic solutions exhibit improved crystalline order in both the alkyl and ?-stacking directions. Due to this improved crystallinity, transistors with active layers cast from lyotropic solutions exhibit a significant improvement in carrier mobility compared to those cast from isotropic solution.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: April 2, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Colin R. Bridges, Michael J. Ford, Guillermo C. Bazan, Rachel A. Segalman
  • Patent number: 10242912
    Abstract: Integrated device dies and methods for forming one or more of the integrated device dies are disclosed. The integrated device dies can be formed using two step sawing process; a first sawing step partially sawing a substrate comprising metal and a second sawing step sawing through a remaining thickness of the substrate.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 26, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Craig Ventola, Robert O. Doherty, Jose A. Santana, John A. McHatton
  • Patent number: 10243041
    Abstract: A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hari V. Mallela, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • Patent number: 10236235
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: March 19, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10230028
    Abstract: A semiconductor light emitting device includes a substrate made of resin, a first wiring and a second wiring formed on the substrate, a light emitting element disposed on the substrate and electrically connected to the first wiring and the second wiring, and a transparent sealing resin configured to seal the light emitting element. The substrate contains an acrylic resin, and the sealing resin contains silicon.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: March 12, 2019
    Assignee: Rohm Co., Ltd.
    Inventors: Hirotaka Obuchi, Junichi Itai
  • Patent number: 10229926
    Abstract: A method for manufacturing a flash memory device includes providing a substrate structure including a substrate, an insulating layer on the substrate, and a stack structure including a charge storage layer, a tunneling dielectric layer, a charge trapping layer, a blocking dielectric layer and a gate layer disposed sequentially from bottom to top on the insulating layer. The method also includes performing a selective nitriding process on the substrate structure to form a nitride layer exposed surfaces of the charge storage layer and the gate layer, and forming an isolation region on side surfaces of the stack structure. The method can mitigate the problem of an undesirable increase in the threshold voltage with an increase in the integration density of the flash memory device.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 12, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Guobin Yu, Xiaoping Xu
  • Patent number: 10224412
    Abstract: A method of fabricating a semiconductor device includes forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 5, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masataka Yoshinari
  • Patent number: 10211220
    Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Il Lee, Kyung Jun Shin, Dong Seog Eun, Ji Hye Kim, Hyun Kook Lee
  • Patent number: 10211092
    Abstract: Fabricating a transistor includes receiving a semiconductor structure including a source/drain, a gate, and a spacer disposed between the source/drain and the gate, a trench contact disposed on the source/drain, a self-aligned cap disposed on the gate, and an interlevel dielectric layer disposed on the spacer, self-aligned cap, and trench contact. A source/drain contact is formed within the interlevel dielectric layer in contact with the trench contact and forming a gate contact in contact with the gate. The interlevel dielectric layer is removed from the spacer, self-aligned cap, and source/drain contact. The self-aligned cap and the spacer is selectively etched. A dielectric liner of a first dielectric material is deposited upon a top of the gate, the trench contact and the S/D contact. The first dielectric material of the dielectric liner pinches off a gap between the gate and the trench contact to form an air spacer therebetween.
    Type: Grant
    Filed: January 28, 2018
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Chanro Park
  • Patent number: 10199365
    Abstract: According to one embodiment, a semiconductor module includes a first circuit component, a first connection member, and a first wire. The first circuit component includes a first substrate, a first conductive layer, a first switching device, and a first diode. The first substrate has an insulation property. The first connection member is provided on a first electrode of the first switching device and the fourth electrode of the first diode, and has a conductive property. The first wire connects the first conductive layer and the first connection member.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: February 5, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akiya Kimura, Tomohiro Iguchi, Akihiro Sasaki
  • Patent number: 10199304
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: February 5, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10199593
    Abstract: A display device comprises: a light emitting array including a plurality of light emitting elements on a substrate and an insulating pattern disposed between the light emitting elements; a color conversion array including a plurality of sub-color conversion parts corresponding to the respective light emitting elements; and a printed circuit board having a first contact electrode connected to each of the light emitting elements, the printed circuit board driving the light emitting elements, wherein the plurality of sub-color conversion parts include first to third sub-color conversion parts that convert the light provided from corresponding light emitting elements into lights of first to third colors and emitting the converted lights, wherein each of the plurality of light emitting elements is electrically insulated from an adjacent light emitting elements.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 5, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang Chul Byun, Hyuk Hwan Kim, Seok Hyun Nam
  • Patent number: 10192961
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region having p type, a second body region having p type, and a JFET region provided between the first body region and the second body region and having n type. The JFET region has both a first impurity capable of providing the p type and a second impurity capable of providing the n type. A concentration of the second impurity is higher than a concentration of the first impurity. The silicon carbide semiconductor device capable of suppressing dielectric breakdown of the gate insulating film is provided.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: January 29, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kosuke Uchida, Toru Hiyoshi, Keiji Wada
  • Patent number: 10193042
    Abstract: A display device is provided. The display device includes a substrate, a driving circuit disposed on the substrate, and a light-emitting unit disposed on the driving circuit and electrically connected to the driving circuit. The light-emitting unit includes a first semiconductor layer, a quantum well layer disposed on the first semiconductor layer and a second semiconductor layer disposed on the quantum well layer. The second semiconductor layer includes a first top surface. The display device also includes a first protective layer disposed on the driving circuit and adjacent to the light-emitting unit. The first protective layer includes a second top surface and a plurality of conductive elements formed therein. The elevation of the first top surface is higher than the elevation of the second top surface.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: January 29, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Tsung-Han Tsai, Kuan-Feng Lee, Yuan-Lin Wu
  • Patent number: 10186503
    Abstract: The module is implemented on a circuit board, the module including a wiring board; an electronic component implemented on a first surface of the wiring board; an external connection electrode formed on a second surface of the wiring board; a solder bump connected to the external connection electrode; a bare chip implemented facedown on the second surface of the wiring board; and a resin covering a surface and a side surface of the bare chip and a side surface of the solder bump on the second surface of the wiring board, wherein a reverse surface of the bare chip and a connection surface of the solder bump are exposed from the resin such that the reverse surface of the bare chip and the connection surface of the solder bump are on a same plane, and wherein the module is implemented on the circuit board so that the reverse surface of the bare chip and the connection surface of the solder bump face the circuit board.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 22, 2019
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventors: Makoto Kitazume, Toshiki Komiyama
  • Patent number: 10177237
    Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: January 8, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita
  • Patent number: 10177038
    Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun Lee, Chung-Ting Ko, Chen-Ming Lee, Mei-Yun Wang, Fu-Kai Yang