Abstract: A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first and second features are electrically isolated from each other; forming an interlayer dielectric layer over the first and second features; and forming a first contact in the interlayer dielectric layer and connected to the first feature and a second contact in the interlayer dielectric layer and connected to the second feature.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a non-silicon thermal conductive component, a silicon layer with a thickness between 100 ? and 10 ?m over the thermal conductive component, a buried oxide (BOX) layer over the silicon layer, an epitaxial layer over the BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the silicon layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

Abstract: A method of manufacturing a light-emitting apparatus includes mounting a first light-emitting element and a second light-emitting element on a substrate. A sealing layer is formed above the first light-emitting element and the second light-emitting element for sealing the first light-emitting element and the second light-emitting element. A first phosphor layer is applied above a first portion of the sealing layer, in which the first phosphor layer includes at least one first phosphor. A second phosphor layer is applied above a second portion of the sealing layer, in which the second phosphor layer includes at least one second phosphor.

Abstract: A method of making a substrate involves patterning the substrate into active areas and dicing lanes. After the substrate is patterned one or more stress layers are formed the substrate. A change in stress along a thickness of the substrate in the active areas is larger than a change in stress along the thickness of the substrate in the dicing lanes. The substrate is subsequently diced along the dicing lanes.

Abstract: An organic light-emitting device includes a first electrode, a first light-emitting layer, a first low work function layer, a second low work function layer, a conductive etching-resistant layer, a first hole-injection layer, a second light-emitting layer, and a second electrode. The first light-emitting layer is disposed over the first electrode. The first low work function layer is disposed over the first light-emitting layer. The second low work function layer is disposed over the first low work function layer, and a work function of the second low work function layer is greater than a work function of the first low work function layer. The conductive etching-resistant layer is disposed over the second low work function layer. The first hole-injection layer is disposed over the conductive etching-resistant layer. The second light-emitting layer is disposed over the first hole-injection layer. The second electrode is disposed over the second light-emitting layer.

Abstract: A multilevel semiconductor device, including: a first level including a first array of first memory cells; a second level including a second array of second memory cells, the first level is overlaid by the second level, where at least one of the first memory cells includes a vertically oriented first transistor, and where at least one of the second memory cells includes a vertically oriented second transistor, and where the first transistor includes a first single crystal channel, and where the second transistor includes a second single crystal channel, and where the first transistor is self-aligned to the second transistor.

Abstract: A multi-chip system includes a top chip stack element comprising a top chip having two major surfaces and top solder pads arrayed along a plane of one of the major surfaces; a bottom chip stack element comprising a bottom substrate having two major surfaces and bottom solder pads arrayed along a plane of one of the major surfaces; one or more solder reservoir pads connected to one or more of the top solder pads or of the bottom solder pads; and solder material; and wherein at least one of the top solder pads is connected to one of the bottom solder pads by one of the solder material.

Abstract: In a method for forming an integrated circuit (IC) structure, which incorporates multiple field effect transistors (FETs) with discrete replacement metal gates (RMGs) and replacement metal contacts (RMCs), gate cut trench(es) and contact cut trench(es) are formed at the same process level. These trench(es) are then filled at the same time with the same isolation material to form gate cut isolation region(s) for electrically isolating adjacent RMGs and contact cut isolation region(s) for electrically isolating adjacent RMCs, respectively. The selected isolation material can be a low-K isolation material for optimal performance. Furthermore, since the same process step is used to fill both types of trenches, only a single chemical mechanical polishing (CMP) process is needed to remove the isolation material from above the gate level, thereby minimizing gate height loss and process variation. Also disclosed herein is an IC structure formed according to the method.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a non-silicon thermal conductive component, a silicon layer with a thickness between 100 ? and 10 ?m over the thermal conductive component, a buried oxide (BOX) layer over the silicon layer, an epitaxial layer over the BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the silicon layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate over the substrate. Besides, the gate include a first portion, a second portion overlying the first portion and a third portion overlying the second portion, and the critical dimension of the second portion is smaller than each of the critical dimension of the first portion and the critical dimension of the third portion.

Abstract: An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support and a front face opposite its rear face. A block is provided for at least partially encapsulating the component above the front face of the support. The device also includes at least one thermal dissipation member having a flexible sheet having at least two portions folded onto one another while forming at least one fold between them, these portions facing one another at least partly.

Abstract: A semiconductor device including a main region, a sense region, a separation region electrically isolating the main and sense region regions includes a first semiconductor layer positioned on the main surface of a semiconductor substrate, a plurality of main cells disposed in the main region, and a plurality of sense cells disposed in the sense region. Source regions of the main cell become conductive with a source electrode and source regions of the sense cell become conductive with a sense electrode. The separation region includes a plurality of second conductivity type separation body regions and a barrier region and is disposed within a first semiconductor layer and is disposed to abut on the surface of the first semiconductor layer.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a non-silicon thermal conductive component, a silicon layer with a thickness between 100 ? and 10 ?m over the thermal conductive component, a buried oxide (BOX) layer over the silicon layer, an epitaxial layer over the BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the silicon layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes an isolation feature over the semiconductor substrate. The fin structure is surrounded by the isolation feature. The semiconductor device structure further includes a gate stack covering the fin structure. In addition, the semiconductor device structure includes a source or drain (S/D) structure covering the fin structure. The semiconductor device structure also includes a conductive contact connected to the S/D structure. The conductive contact includes a first portion and a second portion. The second portion extends from the first portion to the S/D structure. The first portion has a first width adjoining the second portion. The second portion has a second width greater than the first width.

Abstract: Provided are a chip-on-film (COF) semiconductor package capable of improving connection characteristics and a display apparatus including the package. The COF semiconductor package includes a film substrate, a conductive interconnection located on at least one surface of the film substrate and an output pin connected to the conductive interconnection and located at one edge on a first surface of the film substrate, a semiconductor chip connected to the conductive interconnection and mounted on the first surface of the film substrate, a solder resist layer on the first surface of the film substrate to cover at least a portion of the conductive interconnection, and at least one barrier dam on the solder resist layer between the semiconductor chip and the output pin.

Abstract: A vertical superjunction edge termination structure for the drift region of wide bandgap semiconductor devices that provides a low resistance and high off voltage allowing the breakdown voltage of the superjunction drift region to be raised.

Abstract: A silicon carbide single crystal substrate includes a first main surface and a second main surface opposite to the first main surface. The first main surface includes a central square region and an outer square region. When viewed in a thickness direction, each of the central square region and the outer square region has a side having a length of 15 mm. The first main surface has a maximum diameter of not less than 100 mm. The silicon carbide single crystal substrate has a TTV of not more than 5 ?m. A value obtained by dividing a LTIR in the central square region by a LTV in the central square region is not less than 0.8 and not more than 1.2. A value obtained by dividing a LTV in the outer square region by the LTV in the central square region is not less than 1 and not more than 3.

Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a bonding electrode, and a dummy electrode. The first semiconductor substrate has a first surface and a first wiring, and contains a first semiconductor material. The second semiconductor substrate has a second surface and a second wiring, and contains a second semiconductor material, and the first surface and the second surface face each other. The bonding electrode is arranged between the first surface and the second surface, and is electrically connected to the first wiring and the second wiring. The dummy electrode is arranged between the first surface and the second surface, and is electrically insulated from at least one of the first wiring and the second wiring. The bonding electrode has a bonding bump and a first bonding pad. The dummy electrode has a dummy bump and a first dummy pad.

Abstract: An organic light emitting device including an organic light emitting element having a low driving voltage and a high luminous efficiency is provided. The organic light emitting device includes two or more stack emission units, and a charge generating layer including an N-type charge generating layer and a P-type charge generating layer is disposed between the stack emission units. Herein, the P-type charge generating layer is formed of a material having an LUMO energy level similar to an HOMO energy level of a hole transporting layer injected with holes from the P-type charge generating layer. Accordingly, even if the P-type charge generating layer is not additionally doped with a P-type dopant, it is possible to readily inject holes into a stack emission unit adjacent to the P-type charge generating layer.