Abstract: Provided is a memory device including a substrate and a gate structure. The gate structure is located on the substrate. The gate structure includes a stack gate and a selection gate aside the stack structure. A topmost surface of the selection gate is lower than a topmost surface of the stack gate.

Abstract: Separation grooves are etched from a main surface into a semiconductor substrate. The separation grooves separate chip regions in horizontal directions parallel to the main surface. At least some of the separation grooves are spaced from a lateral outer surface of the semiconductor substrate by at most a first distance. An indentation is formed along a lateral surface. The indentation extends from the main surface into the semiconductor substrate. A minimum horizontal indentation width of the indentation is equal to or greater than the first distance. A with respect to the main surface vertical extension of the indentation is equal to or greater than a vertical extension of the separation grooves.

Abstract: A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of non-volatile memory cells includes source diffusion lines and drain diffusion lines, at least one of the source diffusion lines and drain diffusion lines are shared by the first memory cell and the second memory cell, where the first memory cell includes a thin tunneling oxide of less than 1 nm thickness, and where the second memory cell includes a thick tunneling oxide of greater than 2 nm thickness.

Abstract: A high-quality light emitting device is provided which has a long-lasting light emitting element free from the problems of conventional ones because of a structure that allows less degradation, and a method of manufacturing the light emitting device is provided. After a bank is formed, an exposed anode surface is wiped using a PVA (polyvinyl alcohol)-based porous substance or the like to level the surface and remove dusts from the surface. An insulating film is formed between an interlayer insulating film on a TFT and the anode. Alternatively, plasma treatment is performed on the surface of the interlayer insulating film on the TFT for surface modification.

Abstract: A semiconductor device 10 includes: multi-layered substrates 12 each having a circuit board 12c; control terminals 14 whose one end is fixed on the circuit board 12c of each multi-layered substrate 12; a resin case 15 which has openings 20 and is arranged to cover the multi-layered substrates 12, through which openings 20 the other ends of the control terminals 14 extend outwardly; and resin blocks 18 which are each inserted into the openings 20 of the resin case 15 and press-fixes the control terminals 14 against the side walls of the respective openings 20. The control terminals 14 each have a low-rigidity portion 14j at a position that is further interior of the resin case 15 than a position where each control terminal 14 is in contact with the resin block 18 in the respective openings 20 of the resin case 15.

Abstract: A semiconductor device includes a semiconductor substrate having a predetermined region in which a standard cell is disposed, and also includes: a first circuit connected to a first ground power line; a second circuit that is connected to a second ground power line and formed from the standard cells; and a protection circuit interposed and connected between the first circuit and the second circuit. The protection circuit includes: a resistor connected in series between the first circuit and the second circuit; and a protector that is interposed and connected between a node of the resistor on the second circuit side and the second ground power line and clamps a potential difference between the node and the second ground power line to a predetermined voltage or lower. The protection circuit is formed in a protection cell disposed in the predetermined region.

Abstract: A method of manufacturing a semiconductor device includes forming a separation trench into a first main surface of a semiconductor substrate and removing substrate material from a second main surface of the semiconductor substrate, so as to thin the substrate to a thickness of less than 100 ?m, the second main surface being opposite to the first main surface, so as to uncover a bottom side of the trench. Additional methods of manufacturing semiconductor devices are provided.

Abstract: A light emitting diode (LED) panel and a manufacturing method thereof are provided. The LED panel includes: a substrate; and a plurality of subpixel areas formed over a substrate, in which each of the plurality of subpixel areas include: a plurality of pixel electrodes spaced from each other; at least LED formed over the plurality of pixel electrodes; and at least one transistor disposed at one side of at least one of the plurality of pixel electrodes to control at least one of the plurality of pixel electrodes.

Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: A nitride light-emitting diode (LED) fabrication method includes: providing a glass substrate; stacking a buffer layer structure composed of circular SiAlN layers and AlGaN layers with the number of cycles 1-5; growing a non-doped GaN layer, an N-type layer, a quantum well layer and a P-type layer. By using the low-cost glass the substrate that has a mature processing technology, and growing a SiAlN and an AlGaN buffer layer thereon, lattice mismatch constant between the substance and the epitaxial layer can be improved. Therefore, photoelectric property of the LED can be improved.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures including a memory film and a vertical semiconductor channel are formed through the alternating stack in an array configuration. Backside trenches extending along a lengthwise direction are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers. Filling of the backside recesses with electrically conductive layers can be performed without voids or with minimal voids by arranging the memory stack structures with a non-uniform pitch. The non-uniform pitch may be along the direction perpendicular to the lengthwise direction such that the nearest neighbor distance among the memory stack structures is at a minimum between the backside trenches. Alternatively or additionally, the pitch may be modulated along the lengthwise direction to provide wider spacing regions that extend perpendicular to the lengthwise direction.

Abstract: A method for via alignment includes forming first airgaps between interconnect structures and depositing a pinch off layer to close off openings to the first airgaps. A protection layer is formed in divots in the pinch off layer. The protection layer and the pinch off layer are planarized to form a surface where the protection layer remains in the divots. An interlevel dielectric layer (ILD) is deposited on the surface. The ILD and the pinch off layer are etched using the protection layer as an etch stop to align a via and expose the interconnect structure through the via.

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches with deep trench depletion and isolation structures and methods of manufacture. The structure includes a bulk substrate with a fully depleted region below source and drain regions of at least one gate stack and confined by deep trench isolation structures lined with doped material.

Abstract: Memory stack structures can be formed through an alternating stack of insulating layers and spacer material layers that are formed as, or are subsequently replaced with, electrically conductive layers. The memory stack structures can be formed as rows having a first pitch. Additional insulating layers and at least one drain select level dielectric layer are formed over the alternating stack. Drain select level openings are formed in rows having a smaller second pitch. Partial replacement of the at least one drain select level dielectric layer forms spaced apart electrically conductive line structures that surround a respective plurality of drain select level openings. Drain select level channel portions are subsequently formed in respective drain select level openings.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a columnar member, and an insulating film. The stacked body is provided on the substrate, and includes a plurality of electrode layers separately stacked each other. The columnar member is provided in the stacked body, and includes a first semiconductor portion extending in a stacked direction of the plurality of electrode layers. The insulating film covers a bottom portion of the columnar member.

Abstract: In a method for forming an integrated circuit (IC) structure, which incorporates multiple field effect transistors (FETs) with discrete replacement metal gates (RMGs) and replacement metal contacts (RMCs), gate cut trench(es) and contact cut trench(es) are formed at the same process level. These trench(es) are then filled at the same time with the same isolation material to form gate cut isolation region(s) for electrically isolating adjacent RMGs and contact cut isolation region(s) for electrically isolating adjacent RMCs, respectively. The selected isolation material can be a low-K isolation material for optimal performance. Furthermore, since the same process step is used to fill both types of trenches, only a single chemical mechanical polishing (CMP) process is needed to remove the isolation material from above the gate level, thereby minimizing gate height loss and process variation. Also disclosed herein is an IC structure formed according to the method.

Abstract: A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.

Abstract: A method of removing the CESL from small canyon TS structures of a MOSFET device while maintaining gate cap height and the resulting device are provided. Embodiments include providing two gates laterally separated over and perpendicular to a fin of a semiconductor device, each gate having sidewall spacers and a nitride cap; forming a conformal SiN CESL on bottom and side surfaces of a trench formed between opposing spacers between the gates; filling the trench with oxide; planarizing the spacers, nitride caps, oxide, and CESL; removing the oxide; forming a topological flat-SiN layer over the spacers, nitride caps, and CESL; removing the topological flat-SiN layer from side and bottom surfaces of the trench; removing the CESL and the topological flat-SiN layer down to a top surface of the spacers; and performing contact metallization.