Patents Examined by George Goudreau
  • Patent number: 7651949
    Abstract: A semiconductor device may be manufactured by employing an ashing process for removing a photoresist in a process chamber, wherein the ashing process comprises: removing the photoresist for a first predetermined process time by flowing one or more oxygen and nitrogen source gases into the process chamber at first predetermined pressure, power, and temperature conditions; removing a surface portion of a polymer (e.g., from a previous etching process) for a second predetermined process time by flowing a mixture of one or more water source gases (e.g., H2O) and a fluorocarbon (e.g., CF4) into the process chamber at second predetermined pressure, power, and temperature conditions; and removing remaining photoresist for a third predetermined process time by flowing an oxygen source gas (e.g., O2) gas into the process chamber at third predetermined pressure, power, and temperature conditions.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: January 26, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bo-Yeoun Jo
  • Patent number: 7582221
    Abstract: The present invention provides a wafer manufacturing method and a wafer polishing apparatus which enable control of sags in a periphery of a wafer and improvement of nanotopology values thereof that is strongly required recently, and a wafer. In a polishing process for making a mirror surface of the wafer, a back surface of the wafer is polished to produce a reference plane thereof.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: September 1, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Shigeyoshi Netsu, Hisashi Masumura
  • Patent number: 7563722
    Abstract: A method of micro- and nanotexturing of various solid surfaces in plasma where carbon nanotubes are used as an etch mask. The method allows obtaining textures with feature sizes that can be controlled with the nanotube dimensions and the density of coating the treated surface.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: July 21, 2009
    Assignee: Applied Nanotech Holdings, Inc.
    Inventors: Zvi Yaniv, Igor Pavlovsky, Mohshi Yang
  • Patent number: 7557042
    Abstract: Floating gates are formed in two separate polysilicon depositions steps resulting in distinct portions. The first formed portions are between isolation regions. A thick insulator is formed over the isolation regions and floating gate portions. The thick insulator is patterned to leave fences over the isolation regions. A thinning process, an isotropic etch in this example, is applied to these fences to make them thinner. Polysilicon sidewall spacers are formed on the sides of these fences. These sidewall spacers become the second portion of the floating gate. These second portions have the desired shape for significantly increasing the capacitance to the subsequently formed control gates, thereby reducing the gate voltage required for programming and erasing made by a relatively robust process.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: July 7, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chi Nan Brian Li, Cheong M. Hong, Rana P. Singh
  • Patent number: 7550392
    Abstract: A semiconductor device manufacturing method, includes a step of forming a first alumina film (underlying insulating film) 37 on a semiconductor substrate 20, a step of forming a first conductive film 41, a ferroelectric film 42, and a second conductive film 43 in sequence on the first alumina film 37, a step of forming a mask material film 45 on the second conductive film 43, a step of shaping the mask material film 45 into an auxiliary mask 45a, a step of shaping the second conductive film 43 into an upper electrode 43a by an etching using the auxiliary mask 45a and a first resist pattern 46 as a mask, a step of shaping the ferroelectric film 42 into a capacitor dielectric film 42a by patterning, and a step of shaping the first conductive film 41 into a lower electrode 41a by patterning, whereby a capacitor Q is constructed by the lower electrode 41, the capacitor dielectric film 42a, and the upper electrode 43a.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: June 23, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Genichi Komuro, Kenji Kiuchi
  • Patent number: 7544621
    Abstract: A method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal silicide layer, a spacer, a silicon nitride cap layer, and a dielectric layer have been formed. The method includes performing a chemical mechanical polishing process to polish the dielectric layer using the silicon nitride cap layer as a polishing stop layer to expose the silicon nitride cap layer over the gate electrode; removing the exposed silicon nitride cap layer to expose the metal silicide layer; and performing a first etching process to remove the metal silicide layer on the gate electrode.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: June 9, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Kuen Chen, Chih-Ning Wu, Wei-Tsun Shiau, Wen-Fu Yu
  • Patent number: 7544622
    Abstract: A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove native oxide at the bottom of the contact with little effect on the BPSG, the contact is dipped in an etch retardant before being dipped in a cleaning solution containing both the etch retardant and an etchant. The dip in etch retardant modifies the surface of the BPSG, thereby lessening the enhanced etching experienced during the initiation of the dip into the etchant/etch retardant cleaning solution. Results of a etchant/etch retardant clean, both with and without the prepassivation, can be illustrated on a graph depicting the change in contact diameter as a function of dip time. Specifically, the results define “best fit” lines on that graph.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: June 9, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Satish Bedge
  • Patent number: 7514277
    Abstract: An etching method capable of controlling the film thickness of a hard mask layer uniformly is provided. A plasma etching is performed on a native oxide film by using an etching gas containing, for example, CF4 and Ar while a thickness of a silicon nitride film is being monitored and the etching is finished when the thickness of the silicon nitride film reaches a predetermined value. Then, a plasma etching is performed on a silicon substrate by employing an etching gas containing, for example, Cl2, HBr and Ar and using the silicon nitride film as a mask while a depth of a trench is being monitored and the etching is finished when the depth of the trench reaches a specified value.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: April 7, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Susumu Saito, Akitaka Shimizu
  • Patent number: 7509962
    Abstract: A method and control system for treating a hafnium-based dielectric processing system in which a system component of the processing system is exposed to a chlorine-containing gas. A residual hafnium by-product remaining in the processing system after a hafnium removal process is reacted with a chlorine-containing etchant derived from the chlorine-containing gas. A chlorinated hafnium product is volatilized for exhaustion from the processing system. The control system can utilize a computer readable medium to introduce a chlorine-containing gas to the processing system, to adjust at least one of a temperature and a pressure in the processing system to produce from the chlorine-containing gas a chlorine-containing etchant for dissolution of a residual hafnium by-product remaining in the processing system after a hafnium silicate, hafnium oxide, or hafnium oxynitride removal process, and to exhaust a chlorinated hafnium product from the processing system.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: March 31, 2009
    Assignee: Tokyo Electron Limited
    Inventors: David L. O'Meara, Shingo Maku
  • Patent number: 7485241
    Abstract: The invention provides a chemical-mechanical polishing composition comprising: (a) fumed silica particles, (b) about 5×10?3 to about 10 millimoles per kilogram of at least one alkaline earth metal selected from the group consisting of calcium, strontium, barium, and mixtures thereof, based on the total weight of the polishing composition, (c) about 0.1 to about 15 wt. % of an oxidizing agent, and (d) a liquid carrier comprising water. The invention also provides a polishing composition, which optionally comprises an oxidizing agent, comprising about 5×10?3 to about 10 millimoles per kilogram of at least one alkaline earth metal selected from the group consisting of calcium, strontium, and mixtures thereof. The invention further provides methods for polishing a substrate using the aforementioned polishing compositions.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: February 3, 2009
    Assignee: Cabot Microelectronics Corporation
    Inventors: David J. Schroeder, Kevin J. Moeggenborg
  • Patent number: 7481950
    Abstract: A polishing composition of the present invention, which is used in precision polishing the surface of a wafer for semiconductor devices, remarkably reduces haze that occurs on the surface of the wafer. The polishing composition includes silicon dioxide, an alkaline compound, a water-soluble polymer, and water. The silicon dioxide is colloidal silica or fumed silica. The average primary particle diameter DSA of the colloidal silica is from 5 to 30 nm, and the average secondary particle diameter DN4 of the colloidal silica is from 5 to 120 nm. The average primary particle diameter DSA of the fumed silica is from 5 to 30 nm, and the average secondary particle diameter DN4 of the fumed silica is from 5 to 200 nm.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: January 27, 2009
    Assignee: Fujimi Incorporated
    Inventors: Shuhei Yamada, Akihiro Kawase
  • Patent number: 7482279
    Abstract: A method for fabricating a conducting layer pattern using a hard mask of which a upper surface is flattened by the use of ArF exposure light source.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: January 27, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung-Kwon Lee
  • Patent number: 7479458
    Abstract: A method for etching a barrier material on a semiconductor substrate is disclosed. The method includes placing the substrate in a plasma processing chamber of the plasma processing system, wherein the substrate includes the barrier material and a low-k material, and wherein the barrier material and a low-k material are configured to be exposed to a plasma. The method also includes flowing an etchant gas mixture, including CH3F from about 4% to about 8% of a plasma gas flow, into the plasma processing chamber, wherein the etchant gas mixture is configured to etch the barrier material at a first etch rate, the etchant gas mixture is configured to etch the low-k material at a second etch rate, wherein the first etch rate is substantially greater than the second etch rate. The method further includes striking a plasma from the etchant source gas; and etching the barrier layer and the low-k layer.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: January 20, 2009
    Assignee: Lam Research Corporation
    Inventors: Guang-Yaw Hwang, Thomas Nguyen, Wen-Ben Chou, Timothy Tran, Yu-Wei Yang
  • Patent number: 7452819
    Abstract: There is disclosed a chemical mechanical polishing method of an organic film comprising forming the organic film above a semiconductor substrate, contacting the organic film formed above the semiconductor substrate with a polishing pad attached to a turntable, and dropping a slurry onto the polishing pad to polish the organic film, the slurry being selected from the group consisting of a first slurry and a second slurry, the first slurry comprising a resin particle having a functional group selected from the group consisting of an anionic functional group, a cationic functional group, an amphoteric functional group and a nonionic functional group, and having a primary particle diameter ranging from 0.05 to 5 ?m, the first slurry having a pH ranging from 2 to 8, and the second slurry comprising a resin particle having a primary particle diameter ranging from 0.05 to 5 ?m, and a surfactant having a hydrophilic moiety.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: November 18, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Gaku Minamihaba, Yoshikuni Tateyama, Hiroyuki Yano, Atsushi Shigeta
  • Patent number: 7442651
    Abstract: An etching technique capable of applying etching at high selectivity to a transition metal element-containing electrode material layer which is formed on or above a dielectric material layer made of a high-dielectric-constant or “high-k” insulator is provided. To this end, place a workpiece on a lower electrode located within a vacuum processing vessel. The workpiece has a multilayer structure of an electrode material layer which contains therein a transition metal element and a dielectric material layer made of high-k insulator. Then, while introducing a processing gas into the vacuum processing vessel, high-frequency power is applied to inside of the vacuum processing vessel, thereby performing plasma conversion of the introduced processing gas so that the workpiece is etched at its surface. When etching the electrode material layer, an HCl gas is supplied as the processing gas.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: October 28, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Masahito Mori, Toshiaki Nishida, Naoshi Itabashi, Motohiko Yoshigai, Hideyuki Kazumi, Kazutami Tago
  • Patent number: 7439087
    Abstract: A technology for reducing distance between adjacent pixel electrodes to smaller than the limit set by conventional process margin and also preventing adjacent pixel electrodes from being short circuited is provided.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: October 21, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akira Ishikawa, Yoshiharu Hirakata
  • Patent number: 7435356
    Abstract: An aqueous abrasive-free composition is useful for chemical mechanical polishing of a patterned semiconductor wafer containing a nonferrous metal. The composition comprises an oxidizer, an inhibitor for the nonferrous metal, 0 to 15 weight percent water soluble modified cellulose, 0 to 15 weight percent phosphorus compound, 0.005 to 5 weight percent of an amphiphilic polymer, the amphiphilic polymer having an ionic hydrophilic portion with a carbon number of 2 to 250 and water.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: October 14, 2008
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Tirthankar Ghosh, Robert D. Solomon, Hongyu Wang
  • Patent number: 7427362
    Abstract: The polishing solution is useful for removing barrier materials in the presence of at least one nonferrous interconnect metal with limited erosion of dielectrics. The polishing solution contains 0 to 20 weight percent oxidizer, at least 0.001 weight percent inhibitor for reducing removal rate of the nonferrous interconnect metals, 0.0005 to 5 weight percent of at least one nonferrous accelerator selected from the group of a complexing agent for complexing the nonferrous metal and a water-soluble polymer containing an acrylic acid functional group and having a number average molecular weight of 100 to 1,000,000, 0 to 50 weight percent abrasive and balance water at a pH less than 7.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: September 23, 2008
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventor: Zhendong Liu
  • Patent number: 7422020
    Abstract: A porous dielectric layer is formed on a substrate. Aluminum is incorporated in the porous dielectric layer with a pattern process using an Aluminum gas precursor. The incorporated Aluminum improves the mechanical properties of the porous dielectric layer.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Vijayakumar Ramachandrarao, Grant Kloster
  • Patent number: 7419612
    Abstract: The invention concerns a method which consists in first subjecting the polyimide sheet to ionic bombardment, followed by an irradiation in the visible domain and finally a relatively brief chemical etching. Said method enables a thin polyimide sheet comprising pores, of nanometric to micrometric size, having a substantially cylindrical shape and substantially equal diameters to be obtained.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: September 2, 2008
    Assignee: Universite Catholique De Louvain
    Inventors: Roger Legras, Etienne Ferain