Abstract: The invention concerns a method which consists in first subjecting the polyimide sheet to ionic bombardment, followed by an irradiation in the visible domain and finally a relatively brief chemical etching. Said method enables a thin polyimide sheet comprising pores, of nanometric to micrometric size, having a substantially cylindrical shape and substantially equal diameters to be obtained.

Abstract: A slurry system for a chemical mechanical polishing (CMP) process and a method for using the same wherein the slurry system includes an aqueous dispersion comprising at least abrasive polymer containing particles in an alkaline solution having a pH of less than about 9.5; and wherein the method includes providing a semiconductor wafer process surface including a oxide containing material and metal filled semiconductor features; providing the system; and, polishing in a CMP process the semiconductor wafer process surface using the slurry system to remove at least a portion of the oxide containing material and the metal comprising the metal filled semiconductor features.

Abstract: An etching method forms an opening with a substantially vertical profile extending to a stopper layer by performing an etching with a plasma of an etching gas acting on an object to be processed loaded in an evacuable processing vessel, wherein the object has a mask layer of a predetermined pattern, a silicon layer to be etched formed below the mask layer and the stopper layer formed below the silicon layer. The etching method includes a first etching process for forming an opening with a tapered wall surface in the silicon layer by using a first etching gas including a fluorine-containing gas and O2 but not HBr; and a second etching process for etching the opening by using a second etching gas including a fluorine-containing gas, O2 and HBr.

Abstract: A method of controlling a recess etch process for a multilayered substrate having a trench therein and a column of material deposited in the trench includes determining a first dimension from a surface of the substrate to a reference point in the substrate by obtaining a measured net reflectance of at least a portion of the substrate including the trench, computing a modeled net reflectance of the portion of the substrate as a weighted incoherent sum of reflectances from n?1 different regions constituting the portion of the substrate, determining a set of parameters that provides a close match between the measured net reflectance and the modeled net reflectance, and extracting the first dimension from the set of parameters; computing an endpoint of the process as a function of the first dimension and a desired recess depth measured from the reference point; and etching down from a surface of the column of material until the endpoint is reached.

Abstract: The invention concerns a method of wet chemical etching of a wafer comprising at least one surface layer of silicon-germanium (SiGe) for etching by dispensing an etching solution deposited on a rotating wafer, the method being characterized in that it comprises a first etching step in which said etching solution is dispensed from a fixed position located at a predetermined distance from the center of the wafer, and a second etching step in which the etching solution is dispensed radially from the center of the wafer and over a maximum distance which is less than the radius of said wafer.

Abstract: A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.

Abstract: A dry etching method includes loading a wafer on a lower electrode having at least two cooling paths. Cooling fluids having different temperatures are supplied to each of the cooling paths of the lower electrode so that the multiple cooling paths are at different temperatures from one another. The wafer is etched during cooling.

Abstract: A chemical mechanical polishing slurry comprising an oxidizing agent, a complexing agent, an abrasive, and an optional surfactant, as well as a method for using the chemical mechanical polishing slurry to remove copper alloy, titanium, titanium nitride, tantalum and tantalum nitride containing layers from a substrate. The slurry does not include a separate film-forming agent.

Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, is disclosed, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90° from horizontal, with no bowing or notching.

Abstract: To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15b) of the gate electrode 15G.

Abstract: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation layer by using the same mask at a different radiation exposure level to make the opening more narrow than the underlying plug. A conductive line is then formed which makes electrical contact with the plug through the opening in the isolation layer. By vertically separating and electrically isolating the conductive plug from adjacent conductive lines, the isolation layer advantageously reduces the likelihood of an undesired electrical short occurring between the conductive plug and a nearby conductive line.

Abstract: The method for avoiding polysilicon film over etch abnormal includes cleaning a semiconductor substrate. A dielectric layer is formed on the substrate. Subsequently, a first silicon source gas at a first flow rate is next performed injecting into a reaction chamber to form a first polysilicon film over the dielectric layer. Successively, a second silicon source gas at a second flow rate is performed injecting into the reaction chamber to form a second polysilicon film over the first polysilicon film, wherein the second silicon source gas having a different growth rate than the first silicon source gas. A patterned photoresist layer is then formed on the second polysilicon film. After the patterned photoresist layer is formed, a dry etching process by way of using the patterned photoresist layer as a etching mask is performed to etch through in turn the second polysilicon film and the first polysilicon film till exposing to the dielectric layer. Finally, the photoresist layer is removed.

Abstract: A process for the removal of a substance from a substrate for etching and/or cleaning applications is disclosed herein. In one embodiment, there is provided a process for removing a substance having a dielectric constant greater than silicon dioxide from a substrate by reacting the substance with a reactive agent that comprises at least one member from the group consisting a halogen-containing compound, a boron-containing compound, a hydrogen-containing compound, nitrogen-containing compound, a chelating compound, a carbon-containing compound, a chlorosilane, a hydrochlorosilane, or an organochlorosilane to form a volatile product and removing the volatile product from the substrate to thereby remove the substance from the substrate.

Abstract: In a first step and a thirst step, etching gases are used which contain fluorocarbon gases having C/F atom number ratios higher than that in a second step. A hole is formed to a midpoint in a silicon oxide film in the first step, the hole is formed until a base SiN film begins to be exposed or immediately before it is exposed in the second step, and overetching is performed in the third step. This enables even a hole having a fine diameter and a high aspect ratio to be formed in an excellent shape.

Abstract: A method of manufacture includes processing an object in a chamber and subsequently generating an electrical force of attraction to float contaminants off of a region adjacent the processed object before the object is unloaded from the chamber. The object may be processed with the use of plasma. The plasma is produced by introducing a first gas into the chamber and applying a source power to the first gas. The plasma is extinguished after the object is processed with the use of the plasma. Then, a second gas is introduced into the chamber and a source power is applied to the second gas to generate the electrical force of attraction. At this time, the parameters are controlled so that particle contaminants are readily removed without any influence on the object. Also, the same electrode can be used to apply source power to both the first and second gas. Thus, the operation of removing the particle contaminants is relatively simple.

Abstract: The present invention attracts a wafer 6, placed on a susceptor 5, toward the susceptor 5 by the electrostatic attractive power of an electrostatic chuck electrode 7, varies the output voltage of a variable direct current power source 23 for the electrostatic chuck electrode 7 while measuring the temperature of the wafer 6 by a temperature detection sensor 21; and detects the potential of the wafer 6 based on the output voltage of the variable direct current power source 23 at a time when the temperature of the wafer 6 peaks.

Abstract: An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor.

Abstract: Methods and systems for monitoring a parameter of a measurement device during polishing, damage to a specimen during polishing, a characteristic of a polishing pad, or a characteristic of a polishing tool are provided. One method includes scanning a specimen with a measurement device during polishing of a specimen to generate output signals at measurement spots on the specimen. The method also includes determining if the output signals are outside of a range of output signals. Output signals outside of the range may indicate that a parameter of the measurement device is out of control limits. In a different embodiment, output signals outside of the range may indicate damage to the specimen. Another method includes scanning a polishing pad with a measurement device to generate output signals at measurement spots on the polishing pad. The method also includes determining a characteristic of the polishing pad from the output signals.

Abstract: A method for SAC etching is provided involving a) etching a Si wafer having a nitride present thereon with a first etching gas containing a first perfluorocarbon and carbon monoxide, and b) etching the resultant Si wafer having an initially etched nitride photoresist thereon with a second etching gas containing a second perfluorocarbon in the substantial absence of carbon monoxide, wherein the etching steps a) and b) are performed at high RF power and low pressure compared to conventional processes to provide higher selectivity etching and a larger process window for SAC etching, as well as the ability to perform SAC etching and island contact etching under the same conditions with high verticality of the island contact and SAC walls.

Abstract: A new method of patterning the polysilicon layer in the manufacture of an integrated circuit device has been achieved. A polysilicon layer is provided overlying a semiconductor substrate. The polysilicon layer may overlie a gate oxide layer and thereby comprise the polysilicon gate for MOS devices. A hard mask layer is provided overlying the polysilicon layer. A resist layer is provided overlying the hard mask layer. The resist layer is patterned to form a resist mask the exposes a part of the hard mask layer. The polysilicon layer is patterned in a plasma dry etching chamber. First, the resist layer is optionally trimmed by etching. Second, the hard mask layer is etched where exposed by the resist mask to form a hard mask that exposes a part of the polysilicon layer. Third, the resist mask is stripped away. Fourth, polymer residue from the resist mask is cleaned away using a chemistry containing CF4 gas. Fifth, the polysilicon layer is etched where exposed by the hard mask.