Patents Examined by George R. Fourson
  • Patent number: 10923581
    Abstract: A method for manufacturing a semiconductor structure including forming a first type semiconductor layer. The method also includes forming a semiconductor interlayer over the first type semiconductor layer. The method further includes forming a second type semiconductor layer over the semiconductor interlayer. The method further includes etching the first type semiconductor layer, the semiconductor interlayer, and the second type semiconductor layer to form a fin structure. The method further includes oxidizing the semiconductor interlayer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: February 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gerben Doornbos, Peter Ramvall, Matthias Passlack, Carlos H. Diaz
  • Patent number: 10923438
    Abstract: A package structure and method for forming the same are provided. The method includes forming a through substrate via structure in a substrate, and forming a first trench in the substrate. The method includes stacking a first stacked die package structure over the substrate using a plurality of first bonding structures. The first bonding structures are between the substrate and the first stacked die package structure, and a there is plurality of cavities between two adjacent first bonding structures. The method also includes forming an underfill layer over the first stacked die package structure and in the cavities, and the underfill layer is formed in a portion of the first trench. The method further includes forming a package layer over the underfill layer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, I-Ting Huang, Shih-Ting Lin, Szu-Wei Lu
  • Patent number: 10903143
    Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively and disposed between the first active region and the second active region in the second direction. A length of the first gate contact structure and a length of the second gate contact structure in the second direction are less than a length of the isolation structure in the second direction.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: January 26, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Yu-Ruei Chen
  • Patent number: 10896976
    Abstract: A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Henry K. Utomo, Reinaldo Ariel Vega
  • Patent number: 10886318
    Abstract: An image sensor is disclosed. The image sensor may include a semiconductor substrate including a first pixel group region and a second pixel group region, the first pixel group region including first pixel regions to sense a first light, the second pixel group region including second pixel regions to sense a second light, each of the first and second pixel regions arranged in n columns and m rows, a pixel isolation structure disposed in the semiconductor substrate to separate the first and second pixel regions from each other, first and second photoelectric conversion regions disposed in each of the first and second pixel regions of the semiconductor substrate, and a first separation structure disposed in each of the first pixel regions and in the semiconductor substrate between the first and second photoelectric conversion regions. The first separation structure may be spaced apart from the pixel isolation structure.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghyung Pyo, Kyungho Lee
  • Patent number: 10886298
    Abstract: A method of forming a memory device including forming a stack of silicon nitride layers and polysilicon layers that are alternating arranged, etching a serpentine trench in the stack of silicon nitride layers and polysilicon layers, forming a first isolation layer in the serpentine trench, removing one of the silicon nitride layers to form a recess between neighboring two of the polysilicon layers, and forming in sequence a doped polysilicon layer, a gate dielectric layer, and a conductive layer in the recess.
    Type: Grant
    Filed: March 22, 2020
    Date of Patent: January 5, 2021
    Inventor: Chen-Chih Wang
  • Patent number: 10879489
    Abstract: The present invention provides a method of manufacturing an organic device having a protective film, the method including: providing bonding layers (adhesives) on one surface of a first substrate and one surface of a second substrate; providing an organic device on the other surface of the first substrate; and providing the second substrate on the organic device such that the bonding layer (adhesive) provided on the second substrate is in contact with the organic device. Since the organic device having the protective film according to the present invention may be attached to other materials through the bonding layer (adhesive), it is not necessary to apply heat in order to attach the organic device to other materials, and as a result, it is possible to attach the organic device to various materials having various shapes regardless of types and shapes of materials.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: December 29, 2020
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Kyung Cheol Choi, Yong Min Jeon
  • Patent number: 10879217
    Abstract: A multi-color light emitting pixel unit includes a first type of light emitting transistor formed on a substrate and including a first segment of a first metal layer and a first segment of a first type of light emitting layer in an order from bottom to top, and a second type of light emitting transistor formed on the substrate and including a second segment of the first metal layer, a second segment of the first type of light emitting layer, a first segment of a second metal layer, a first segment of a second type of light emitting layer in an order from bottom to top, and a first electrical connector connecting the second segment of the first metal layer and the first segment of the second metal layer.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: December 29, 2020
    Assignee: Jade Bird Display (Shanghai) Limited
    Inventors: Qiming Li, Qunchao Xu
  • Patent number: 10868016
    Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: December 15, 2020
    Assignee: SAMSUNG ELECTRONICS., LTD.
    Inventors: Dong-Hyun Im, Daehyun Kim, Hoon Park, Jae-Hong Seo, Chunhyung Chung, Jae-Joong Choi
  • Patent number: 10867841
    Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsuan Hsiao, Yee-Chia Yeo, Tung Ying Lee, Chih Chieh Yeh
  • Patent number: 10861944
    Abstract: According to one embodiment, a semiconductor device includes a first layer, a first electrode, and a first nitride region. The first layer includes a first material and a first partial region. The first material includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The first partial region is of a first conductivity type. The first conductivity type is one of an n-type or a p-type. A direction from the first partial region toward the first electrode is aligned with a first direction. The first nitride region includes Alx1Ga1-x1N (0?x1<1), is provided between the first partial region and the first electrode, is of the first conductivity type, and includes a first protrusion protruding in the first direction.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: December 8, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Hisashi Yoshida, Tatsuo Shimizu, Ryosuke Iijima
  • Patent number: 10861855
    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: December 8, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin
  • Patent number: 10854508
    Abstract: An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chung-Wen Wu, Shiu-Ko Jangjian, Chien-Wen Chiu, Chien-Chung Chen
  • Patent number: 10854471
    Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Tsan-Chun Wang, Liang-Yin Chen, Jing-Huei Huang, Lun-Kuang Tan, Huicheng Chang
  • Patent number: 10854507
    Abstract: A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10847540
    Abstract: A 3D memory device, the device including: a first horizontal bit-line; a second horizontal bit-line disposed above the first horizontal bit-line, where the first horizontal bit-line and the second horizontal bit-line function as a source or a drain for a plurality of parallel vertically-oriented memory transistors, where the first horizontal bit-line and the second horizontal bit-line are self-aligned being formed following the same lithography step; and conductive memory control lines, where a first portion of the conductive memory control lines are disposed at least partially directly underneath the plurality of parallel vertically-oriented memory transistors, and where a second portion of the conductive memory control lines are disposed at least partially directly above the plurality of parallel vertically-oriented memory transistors.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: November 24, 2020
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Patent number: 10845663
    Abstract: An array board 11b includes a display section AA, a source line 20 connected to the display section AA, a test circuit 40 connected to the source line 20 and configured to test the display section AA, a panel-side image input terminal that is disposed such that the test circuit 40 is between the terminal and the display section AA and to which a signal to be supplied to the source line 20 is input, a terminal connection line 51 connecting the source line 20 to the pane-side image input terminal 35A and the terminal connection line 51 including the terminal connection line 51 at least a part of which overlaps the test circuit 40 and a flattening film (insulation film) 28 at least disposed between an overlapping portion of the test circuit 40 and the terminal connection line 51.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: November 24, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 10840252
    Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: November 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junhyoung Kim, Kwang-Soo Kim, Bonghyun Choi, Siwan Kim
  • Patent number: 10833088
    Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Hyun Im, Daehyun Kim, Hoon Park, Jae-Hong Seo, Chunhyung Chung, Jae-Joong Choi
  • Patent number: 10832970
    Abstract: A method for manufacturing a vertical transistor device includes respectively forming a first and second plurality of fins in first and second device regions on a substrate. A plurality of bottom source/drain regions are formed adjacent lower portions of each of the fins, and a sacrificial layer is formed in the first device region on a first bottom source/drain region of the plurality of bottom source/drain regions. In the method, gate structures are formed on the bottom source/drain regions and sacrificial layer, and portions of the gate structures are removed to expose the sacrificial layer in the first device region and a second bottom source/drain region of the plurality of bottom source/drain regions in the second device region. The method further includes depositing a germanium oxide layer on the exposed sacrificial layer and second bottom source/drain region, and converting the germanium oxide layer to a plurality of silicide/germanide layers.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: ChoongHyun Lee, Kangguo Cheng, Juntao Li, Peng Xu