Patents Examined by George R. Fourson
  • Patent number: 10861944
    Abstract: According to one embodiment, a semiconductor device includes a first layer, a first electrode, and a first nitride region. The first layer includes a first material and a first partial region. The first material includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The first partial region is of a first conductivity type. The first conductivity type is one of an n-type or a p-type. A direction from the first partial region toward the first electrode is aligned with a first direction. The first nitride region includes Alx1Ga1-x1N (0?x1<1), is provided between the first partial region and the first electrode, is of the first conductivity type, and includes a first protrusion protruding in the first direction.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: December 8, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Hisashi Yoshida, Tatsuo Shimizu, Ryosuke Iijima
  • Patent number: 10861855
    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: December 8, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin
  • Patent number: 10854508
    Abstract: An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chung-Wen Wu, Shiu-Ko Jangjian, Chien-Wen Chiu, Chien-Chung Chen
  • Patent number: 10854471
    Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Tsan-Chun Wang, Liang-Yin Chen, Jing-Huei Huang, Lun-Kuang Tan, Huicheng Chang
  • Patent number: 10854507
    Abstract: A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10847540
    Abstract: A 3D memory device, the device including: a first horizontal bit-line; a second horizontal bit-line disposed above the first horizontal bit-line, where the first horizontal bit-line and the second horizontal bit-line function as a source or a drain for a plurality of parallel vertically-oriented memory transistors, where the first horizontal bit-line and the second horizontal bit-line are self-aligned being formed following the same lithography step; and conductive memory control lines, where a first portion of the conductive memory control lines are disposed at least partially directly underneath the plurality of parallel vertically-oriented memory transistors, and where a second portion of the conductive memory control lines are disposed at least partially directly above the plurality of parallel vertically-oriented memory transistors.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: November 24, 2020
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Patent number: 10845663
    Abstract: An array board 11b includes a display section AA, a source line 20 connected to the display section AA, a test circuit 40 connected to the source line 20 and configured to test the display section AA, a panel-side image input terminal that is disposed such that the test circuit 40 is between the terminal and the display section AA and to which a signal to be supplied to the source line 20 is input, a terminal connection line 51 connecting the source line 20 to the pane-side image input terminal 35A and the terminal connection line 51 including the terminal connection line 51 at least a part of which overlaps the test circuit 40 and a flattening film (insulation film) 28 at least disposed between an overlapping portion of the test circuit 40 and the terminal connection line 51.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: November 24, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 10840252
    Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: November 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junhyoung Kim, Kwang-Soo Kim, Bonghyun Choi, Siwan Kim
  • Patent number: 10833088
    Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Hyun Im, Daehyun Kim, Hoon Park, Jae-Hong Seo, Chunhyung Chung, Jae-Joong Choi
  • Patent number: 10830544
    Abstract: A self-healing metal structure is provided for transferring heat between an electronics component and a substrate. The self-healing metal structure includes a base metal structural component. A phase change material is provided adjacent at least a portion of the base metal structural component. A protective component at least partially encapsulates the phase change material. Upon the presence of a spatial defect in the base metal structural component, the phase change material reacts with the base structural component to form an intermetallic compound to at least partially occupy the spatial defect. The phase change material at least partially encapsulated with the protective component may be disposed within the base metal structural component as a plurality of separate capsules incorporated therein, or the phase change material at least partially surrounds the base metal structural component.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 10, 2020
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shailesh N. Joshi, Naoya Take
  • Patent number: 10832970
    Abstract: A method for manufacturing a vertical transistor device includes respectively forming a first and second plurality of fins in first and second device regions on a substrate. A plurality of bottom source/drain regions are formed adjacent lower portions of each of the fins, and a sacrificial layer is formed in the first device region on a first bottom source/drain region of the plurality of bottom source/drain regions. In the method, gate structures are formed on the bottom source/drain regions and sacrificial layer, and portions of the gate structures are removed to expose the sacrificial layer in the first device region and a second bottom source/drain region of the plurality of bottom source/drain regions in the second device region. The method further includes depositing a germanium oxide layer on the exposed sacrificial layer and second bottom source/drain region, and converting the germanium oxide layer to a plurality of silicide/germanide layers.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: ChoongHyun Lee, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10826004
    Abstract: The present disclosure describes a flexible display panel and display apparatus. The flexible display panel comprises: a flexible substrate; an array layer located on the flexible substrate; a display layer located on a side of the array layer facing away from the flexible substrate, the display layer comprising a plurality of light-emitting devices; a shielding film located on a side of the flexible substrate facing away from the array layer; the flexible display panel comprises a bendable area, the shielding film has a plurality of hollow portions at least at the bendable area. The present disclosure can shield the film to relieve the bending stress when the flexible display panel is bent, thereby avoiding the crease of the flexible display panel in the bending area, and achieving performance reliability of the flexible display panel.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: November 3, 2020
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventor: Yingteng Zhai
  • Patent number: 10825737
    Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun Lee, Chung-Ting Ko, Chen-Ming Lee, Mei-Yun Wang, Fu-Kai Yang
  • Patent number: 10811519
    Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chang Huang, Fu-Peng Lu, Chun-Chang Liu, Chen-Chiu Huang
  • Patent number: 10808172
    Abstract: A perovskite luminescent nanocrystal has a chemical formula represented by: Cs4BX6, wherein B includes one or more selected from the group consisting of Ge, Pb, Sn, Sb, Bi, Cu, and Mn, and X includes one or more selected from the group consisting of Cl, Br, and I, wherein the Cs4BX6 perovskite luminescent nanocrystal has a pure phase, and a molar ratio of Cs to B (Cs/B) in the Cs4BX6 perovskite luminescent nanocrystal is greater than 1 and less than 4.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: October 20, 2020
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Zhen Bao, Yu-Jui Tseng, Ru-Shi Liu, Hung-Chun Tong, Hung-Chia Wang, Yu-Chun Lee, Tzong-Liang Tsai
  • Patent number: 10811516
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Che-Cheng Chang, Mu-Tsang Lin, Tung-Wen Cheng, Zhe-Hao Zhang
  • Patent number: 10811512
    Abstract: A method of fabricating a semiconductor device includes forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: October 20, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masataka Yoshinari
  • Patent number: 10804175
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: October 13, 2020
    Assignee: MONOLITH SEMICONDUCTOR, INC.
    Inventors: Kevin Matocha, John Nowak, Kiran Chatty, Sujit Banerjee
  • Patent number: 10804402
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Shih-Wei Peng, Wei-Cheng Lin, Lei-Chun Chou
  • Patent number: 10804401
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fang Chen, Jhon Jhy Liaw