Patents Examined by George R. Fourson
  • Patent number: 10741748
    Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph F. Maniscalco, Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang
  • Patent number: 10727069
    Abstract: A semiconductor device and a method of forming the semiconductor device are disclosed. A method includes forming a gate stack over a semiconductor structure. The gate stack is recessed to form a first recess. A first dielectric layer is formed along a bottom and sidewalls of the first recess, the first dielectric layer having a first etch rate. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a second etch rate, the first etch rate being higher than the second etch rate. A third dielectric layer is formed over the second dielectric layer. An etch rate of a portion of the third dielectric layer is altered. The first dielectric layer, the second dielectric layer, and the third dielectric layer are recessed to form a second recess. A capping layer is formed in the second recess.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bang-Tai Tang, Tai-Chun Huang
  • Patent number: 10727110
    Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsuan Hsiao, Yee-Chia Yeo, Tung Ying Lee, Chih Chieh Yeh
  • Patent number: 10705398
    Abstract: An array board 11b includes a display section AA, a source line 20 connected to the display section AA, a test circuit 40 connected to the source line 20 and configured to test the display section AA, a panel-side image input terminal that is disposed such that the test circuit 40 is between the terminal and the display section AA and to which a signal to be supplied to the source line 20 is input, a terminal connection line 51 connecting the source line 20 to the pane-side image input terminal 35A and the terminal connection line 51 including the terminal connection line 51 at least a part of which overlaps the test circuit 40 and a flattening film (insulation film) 28 at least disposed between an overlapping portion of the test circuit 40 and the terminal connection line 51.
    Type: Grant
    Filed: December 22, 2019
    Date of Patent: July 7, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 10707381
    Abstract: A light-emitting diode includes a light-emitting epitaxial laminated layer having a first surface and a second, opposing, surface, including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer; an omnidirectional reflector structure formed on the second surface of the light-emitting epitaxial laminated layer, including a transparent dielectric layer located on the second surface of the light-emitting epitaxial laminated layer and having conductive holes therein; a first transparent adhesive layer on one side surface of the transparent dielectric layer that is distal from the light-emitting epitaxial laminated layer; a second transparent adhesive layer on one side surface of the first transparent adhesive layer that is distal from the transparent dielectric layer; and a metal reflective layer on one side surface of the second transparent adhesive layer that is distal from the first transparent adhesive layer.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 7, 2020
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Cheng Meng, Yuehua Jia, Jing Wang, Chun-Yi Wu, Ching-Shan Tao, Duxiang Wang
  • Patent number: 10707168
    Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Amruthavalli Pallavi Alur, Sri Ranga Sai Boyapati, Robert Alan May, Islam A. Salama, Robert L. Sankman
  • Patent number: 10699985
    Abstract: An electronic device according to various embodiments of the present disclosure includes a housing, a printed circuit board located inside the housing, an electrical element mounted on the printed circuit board, and a shield can that covers the electrical element. A recess area is formed on at least a portion of the shield can, and a metal structure is mounted in the recess area to cool heat generated by the electrical element.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Ho Chung, Soo Ho Noh, Jin Seok Park, Se Young Jang
  • Patent number: 10692869
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The disclosed semiconductor device includes a plurality of gain-cell memory cells each stacked over a substrate. Axes of channel length directions of write transistors of memory cells correspond to each other, and are substantially perpendicular to the top surface of the substrate. The semiconductor device can retain multi-level data. The channel of read transistors is columnar silicon (embedded in a hole penetrating gates of the read transistors). The channel of write transistors is columnar metal oxide (embedded in a hole penetrating the gates of the read transistors and gates, or write word lines, of the write transistors). The columnar silicon faces the gate of the read transistor with an insulating film therebetween. The columnar metal oxide faces the write word line with an insulating film, which is obtained by oxidizing the write word line, therebetween, and is electrically connected to the gate of the read transistor.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 23, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Yoshiyuki Kurokawa
  • Patent number: 10692915
    Abstract: An imaging device includes a first substrate including a photoelectric conversion layer that includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type and in which a plurality of photoelectric conversion units are provided; a second substrate that is joined to the first substrate and in which a readout circuit substrate that outputs a signal based on information detected by the plurality of photoelectric conversion units is provided; and an element isolation portion defined by a first opening provided so as to penetrate the second substrate and at least one of the first semiconductor layer and the second semiconductor layer, and each of the plurality of photoelectric conversion units is separated from each other by the element isolation portion.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: June 23, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takahiro Yajima
  • Patent number: 10686126
    Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINESS CORPORATION
    Inventors: Joseph F. Maniscalco, Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang
  • Patent number: 10679975
    Abstract: The present invention relates to a lighting device comprising a plurality of light emitting diodes, LEDs. The plurality of LEDs is disposed on a substrate for emitting visible light from at least one first light output surface in an outgoing light direction. The lighting device includes also at least one ultra violet light emitting diode, UV LED, for emitting UV light from a second light output surface in the outgoing light direction. A phosphor layer is disposed on at least the plurality of LEDs such that the LEDs are covered by the phosphor layer. The second light output surface for emitting UV light from the at least one UV LED is mounted at a higher level than the at least first light output surface relative to the substrate in the outgoing light direction. The present invention also relates to a method for manufacturing the lighting device.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 9, 2020
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Rifat Ata Mustafa Hikmet, Ties Van Bommel
  • Patent number: 10658365
    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 19, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin
  • Patent number: 10658492
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu, Bao-Ru Young
  • Patent number: 10644024
    Abstract: A transistor includes a substrate having a plurality of source/drain regions and a channel region between the source/drain regions, a gate, and a gate dielectric layer between the gate and the substrate. The substrate tapers in a direction away from the gate dielectric layer in top view. The transistor density can be improved.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: May 5, 2020
    Inventor: Chen-Chih Wang
  • Patent number: 10644104
    Abstract: A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari V. Mallela, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • Patent number: 10644041
    Abstract: This disclosure discloses an array substrate, a method for making the same, and a display apparatus. The array substrate comprises a display area and a peripheral area around the display area. The method comprises: forming an active layer of a low temperature polysilicon TFT in the peripheral area of the array substrate; forming a gate of a oxide TFT disposed in the same layer as a source and a drain of the low temperature polysilicon TFT in the display area of the array substrate, and forming an active layer of the oxide TFT electrically insulated from the gate of the oxide TFT above the gate of the oxide TFT; forming a source and a drain of the oxide TFT on the active layer of the oxide TFT.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: May 5, 2020
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yongqiang Zhang, Jun Fan
  • Patent number: 10636798
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: April 28, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Shan Su, Chia-Wei Wu, Ting-Pang Chung
  • Patent number: 10629802
    Abstract: A magnetoresistance device is disclosed, comprising a bottom electrode, a magnetic tunneling junction (MTJ) disposed on the bottom electrode, a top electrode disposed on the magnetic tunneling junction, a first spacer disposed on the magnetic tunneling junction and covering a sidewall of the top electrode, and a second spacer disposed on the first spacer and conformally covering along a sidewall of the first spacer, a sidewall of the magnetic tunneling junction and a sidewall of the bottom electrode.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Jung Chiu, Yu-Chun Chen, Ya-Sheng Feng, Hung-Chan Lin
  • Patent number: 10626245
    Abstract: Provided are an adhesive film, and an organic electronic device (OED) encapsulation product using the same. Dimensional stability, lifespan, and durability may be enhanced even when a panel of an organic electronic device is large-sized and formed as a thin film by controlling dimensional tolerance and edge angular tolerance of the adhesive film, thereby ensuring long-term reliability, and process yields may be enhanced when the adhesive film is applied to an automation process.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: April 21, 2020
    Assignee: LG Chem, Ltd.
    Inventors: Seung Min Lee, Suk Ky Chang, Hyun Jee Yoo, Jung Sup Shim, Yoon Gyung Cho, Kyung Yul Bae
  • Patent number: 10622365
    Abstract: A semiconductor device, the device including: a plurality of memory cells; and peripheral circuits, the peripheral circuits include controlling the plurality of memory cells, where each of the plurality of memory cells includes a first gate and a second gate, where the plurality of memory cells each include a channel region, at least one channel facet, a charge trap region and a tunneling region, where a portion of the peripheral circuits are designed to control the first gate and the second gate so to position two distinct memory sites, a first memory site and second a memory site, within the charge trap region of the at least one channel facet of at least one of the plurality of memory cells, and where the first memory site is substantially closer to the first gate than the second memory site.
    Type: Grant
    Filed: April 7, 2019
    Date of Patent: April 14, 2020
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Jin-Woo Han