Patents Examined by George R Fourson, III
  • Patent number: 10446614
    Abstract: The present disclosure relates to an organic light-emitting display device capable of improving the aperture ratio thereof, and the organic light-emitting display device according to the present disclosure includes a plurality of sub-pixels respectively including organic emission layers arranged on a substrate, wherein a sub-pixel in which the organic emission layer is spaced a first vertical distance from the substrate and a sub-pixel in which the organic emission layer is spaced a second vertical distance from the substrate are alternatively arranged, thereby improving the aperture ratio.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: October 15, 2019
    Assignee: LG Display Co., Ltd.
    Inventor: Hee-Young Chae
  • Patent number: 10446467
    Abstract: Disclosed are exemplary embodiments of thermal transfer/management and electromagnetic interference (EMI) shielding/mitigation solutions, systems, and/or assemblies for electronic devices. Also disclosed are methods of making or manufacturing (e.g., stamping, drawing, etc.) components of the thermal transfer/management and EMI shielding/mitigation solutions, systems, and/or assemblies.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: October 15, 2019
    Assignee: Laird Technologies, Inc.
    Inventor: Sri Talpallikar
  • Patent number: 10437119
    Abstract: A liquid crystal display device includes: a first display panel; and a second display panel opposing to the first display panel. Each of the first and second display panel includes a plurality of source lines, a plurality of gate lines, a plurality of thin film transistors, and a plurality of pixel electrodes electrically connected to corresponding one of the thin film transistors. In a second display panel, at least two thin film transistors are electrically connected to a same second source line and a same second gate line.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 8, 2019
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Ikuko Mori, Teruhisa Nakagawa, Kazuhiko Tsuda, Katsuji Tanaka
  • Patent number: 10431523
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 1, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10424549
    Abstract: A method of forming a trench structure is provided. The method includes depositing a silicon carbide (SiC) layer on a top metal layer, forming a first passivation layer on the SiC layer, removing a portion of the first passivation layer to form a first opening, forming a second passivation layer on the first passivation layer, the second passivation layer including a first portion in the first opening, and forming a second opening by removing a part of the first portion of the second passivation layer. The forming the second opening exposes the top metal layer.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: September 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Chiang Kuo, Shih-Chi Kuo, Tsung-Hsien Lee, Ying-Hsun Chen
  • Patent number: 10424591
    Abstract: In a memory cell region of a semiconductor device, a memory active region is defined by an element isolation insulating film. In the memory cell region, the position of the upper surface of the element isolation insulating film is set to be lower than the position of the main surface of a semiconductor substrate. A buried silicon nitride film and an etching stopper film are formed over the element isolation insulating film. The position of the upper surface of the etching stopper film is higher than that of the upper surface of the element isolation insulating film defining a peripheral active region.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: September 24, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tamotsu Ogata
  • Patent number: 10418334
    Abstract: A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die. The recesses may be formed by a laser or photolithographic processes in the kerf area between semiconductor die. Once formed, the corner recesses prevent cracking and damage to semiconductor die which could otherwise occur at the corners of adjacent semiconductor die as the adjacent semiconductor die move relative to each other during the backgrind process.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: September 17, 2019
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Hang Zhang, Weili Wang, Junrong Yan, Kim Lee Bock, Chee Keong Chin, Chong Un Tan, Xin Tian
  • Patent number: 10418369
    Abstract: A multilevel semiconductor device including: a first level including a first array of first memory cells and first control line; a second level including a second array of second memory cells and second control line; a third level including a third array of third memory cells and third control line, where the second level overlays the first, and where the third level overlays the second; a first, second and third access pillar; memory control circuits designed to individually control cells of the first, second and third memory cells, where the device includes an array of units, where each of the units includes a plurality of the first, second and third memory cells, and a portion of the memory control circuits, where the array of units include at least eight rows and eight columns of units, and where the memory control is designed to control independently each of the units.
    Type: Grant
    Filed: May 26, 2018
    Date of Patent: September 17, 2019
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Patent number: 10418517
    Abstract: Resonant optical cavity light emitting devices are disclosed, where the device includes a substrate, a first spacer region, a light emitting region, a second spacer region, and a reflector. The light emitting region is configured to emit a target emission deep ultraviolet wavelength, and is positioned at a separation distance from the reflector. The reflector may have a metal composition comprising elemental aluminum or may be a distributed Bragg reflector. The device has an optical cavity comprising the first spacer region, the second spacer region and the light emitting region, where the optical cavity has a total thickness less than or equal to K·?/n. K is a constant ranging from 0.25 to less than 1, ? is the target wavelength, and n is an effective refractive index of the optical cavity at the target wavelength.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 17, 2019
    Assignee: Silanna UV Technologies Pte Ltd
    Inventor: Petar Atanackovic
  • Patent number: 10411163
    Abstract: A light-emitting diode includes a light-emitting epitaxial laminated layer and an omnidirectional reflector structure. The light-emitting epitaxial laminated layer has a first surface and an opposing second surface, including an n-type semi-conductive layer, a light emitting layer and a p-type semiconductor layer.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: September 10, 2019
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Cheng Meng, Yuehua Jia, Jing Wang, Chun-Yi Wu, Ching-Shan Tao, Duxiang Wang
  • Patent number: 10411089
    Abstract: A semiconductor device includes a substrate including a recess, the recess being positioned below an isolation region and having a side portion including a plurality of stepped portions, a plurality of gate electrodes spaced apart from each other on the substrate, and stacked in a direction perpendicular to an upper surface of the substrate, a channel structure passing between a first set of the plurality of gate electrodes, and the isolation region passing between a second set of the plurality of gate electrodes, the isolation region extending from the upper surface of the substrate and having an inclined lateral surface.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jee Yong Kim, Jung Hwan Lee
  • Patent number: 10411110
    Abstract: A semiconductor structure including a substrate, a BJT, a first interconnect structure and a second interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The BJT is located at the first side. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. The first interconnect structure is located at the first side and electrically connected to the base. The second interconnect structure is located at the second side and electrically connected to the collector. The first interconnect structure further extends to the second side. The first interconnect structure and the second interconnect structure are respectively electrically connected to an external circuit at the second side. The semiconductor structure can have better overall performance.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 10, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang
  • Patent number: 10403736
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu, Bao-Ru Young
  • Patent number: 10403620
    Abstract: To provide a semiconductor device capable of restricting the substrate bias effect of a high-side transistor while enhancing the heat radiation property of a low-side transistor. A high-side NMOS transistor 101 is formed in a region S1 on the surface of a SOI substrate 30. A trench 41 surrounds the high-side NMOS transistor 101. SiO2 (first insulator) embeds the trench 41. A low-side NMOS transistor 102 is formed in a region S2 on the surface of the SOI substrate 30 around the trench 41. The side face Sf connecting the region S2 forming the low-side NMOS transistor 102 therein and the backside of the SOI substrate 30 is exposed.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: September 3, 2019
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Shinichirou Wada, Katsumi Ikegaya
  • Patent number: 10395983
    Abstract: A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 27, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10388906
    Abstract: An organic electro-luminescence (EL) element includes a first electrode, a light emitting layer, and a second electrode layered in this order above a substrate. At least one of the first electrode and the second electrode is a light transmissive electrode. The light transmissive electrode includes a base metal layer and a silver thin film. The base metal layer is a metal layer including an alkali metal or an alkaline earth metal as a material. The silver thin film is silver or a silver alloy including silver as a main component, and is disposed on and in contact with the base metal layer.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 20, 2019
    Assignee: JOLED INC.
    Inventors: Jun Yamaguchi, Kenji Harada, Masahiro Tanaka
  • Patent number: 10381289
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: August 13, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10381397
    Abstract: A nano-metallic-planar-apex optical detector, comprising a semiconductor optical detector and a nano array mask defining a plurality of polygonal apertures connected to the optical detector, wherein the semiconductor optical detector detects near-field light focused b the nano array.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: August 13, 2019
    Assignee: Black Sesame International Holding Limited
    Inventors: Zhaowei Xin, Dong Wei
  • Patent number: 10381487
    Abstract: A thin film transistor includes a channel section formed from semiconductor material, a source electrode connected to one end of the channel section, a drain electrode connected to another end of the channel section, an upper gate electrode included in an upper layer than the channel section and overlapping the channel section, a lower gate electrode included in a lower layer than the channel section and overlapping the channel section, an upper gate insulation film disposed between the upper gate electrode and the channel section, and a lower gate insulation film disposed between the lower gate electrode and the channel section and having a film thickness relatively greater than that of the upper gate insulation film.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 13, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kengo Hara, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Teruyuki Ueda
  • Patent number: 10373959
    Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Hyun Im, Daehyun Kim, Hoon Park, Jae-Hong Seo, Chunhyung Chung, Jae-Joong Choi