Abstract: The light emitting diode display apparatus including a first substrate, a plurality of light emitting diodes, an adhesive layer, a color layer, and a second substrate is provided. The first substrate has a plurality of switching elements. The light emitting diode includes a first semiconductor layer, a plurality of second semiconductor layers, a plurality of light emitting layers, a first electrode, and a plurality of second electrodes. The first electrode is disposed on the first semiconductor layer. The second electrodes are respectively disposed on the corresponding second semiconductor layers. Each of the second electrodes is electrically connected to the corresponding switching element. The adhesive layer and the first substrate are respectively located at two opposite sides of the light emitting diode. The color layer is disposed on the first substrate and covers the adhesive layer and the light emitting diode. The second substrate is disposed opposite to the first substrate.

Abstract: A semiconductor layer having an opening and a MEMS resonator formed in the opening is disposed between first and second substrates to encapsulate the MEMS resonator. An electrical contact that extends from the opening to an exterior of the MEMS device is formed at least in part within the semiconductor layer and at least in part within the first substrate.

Abstract: In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A light emitting device including a substrate, a first semiconductor layer, a mesa disposed thereon and including a second semiconductor layer and an active layer, a first contact electrode contacting the first semiconductor layer exposed around the mesa, a second contact electrode contacting the second semiconductor layer, a passivation layer covering the first contact electrode, the mesa, and the second contact electrode and having openings disposed on the first and second contact electrodes, and first and second bump electrodes electrically connected to the first and second contact electrodes through the openings, respectively, in which the mesa has indentations in plan view, the first contact electrode is spaced apart from the mesa by a predetermined distance, surrounds the mesa, and contacts the first semiconductor layer in the indentations, and each of the first and second bump electrodes covers one of the openings of the passivation layer and a portion thereof.

Abstract: A butted contact structure is provided. In one embodiment, a structure includes a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer being disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer being disposed between the second gate and the second source or drain region. The structure includes a butted contact disposed above and extending from the first source or drain region to at least one of the first or second gate, a portion of the first gate spacer extending a distance into the butted contact to separate a first bottom surface of the butted contact from a second bottom surface of the butted contact.

Abstract: A light-emitting device includes: a substrate comprising a first side; multiple semiconductor stacks on the first side and separated from each other, wherein each of the multiple semiconductor stacks comprises a light extraction area; multiple electrode pads on the multiple semiconductor stacks; and a blocking layer between one of the semiconductor stacks and the substrate. The multiple semiconductor stacks comprises a first semiconductor stack and a second semiconductor stack, and the first semiconductor stack and the second semiconductor stack are independently controlled to emit light.

Abstract: A thermal bonding sheet includes a pre-sintering layer containing copper particles and polycarbonate.

Abstract: A display device is provided. The display device includes a substrate, a driving circuit disposed on the substrate, and a light-emitting unit disposed on the driving circuit and electrically connected to the driving circuit. The light-emitting unit includes a first semiconductor layer, a quantum well layer disposed on the first semiconductor layer and a second semiconductor layer disposed on the quantum well layer. The second semiconductor layer includes a first top surface. The display device also includes a first protective layer disposed on the driving circuit and adjacent to the light-emitting unit. The first protective layer includes a second top surface and a plurality of conductive elements formed therein. The elevation of the first top surface is higher than the elevation of the second top surface.

Abstract: A trench power transistor includes a semiconductor body having opposite first and second surfaces, and including at least one active region. Such region includes a trench electrode structure, a well, and a source. The trench electrode structure has an electrode trench recessed from the first surface, and includes first, second, and third insulating layers sequentially disposed over bottom and surrounding walls of the electrode trench, a shield electrode enclosed by the third insulating layer, a fourth insulating layer disposed on the first, second, and third insulating layers, and a gate electrode surrounded by the fourth insulating layer. The second insulating layer made of a nitride material and the fourth insulating layer are different in material. A production method of the transistor is also disclosed.

Abstract: This CIP application builds on Ge quantum dot superlattice (QDSL) based field effect transistors where Ge quantum dot arrays are used as a high carrier mobility channel. The QDSL diodes claims that were withdrawn are included. The diodes are used as light emitting devices and photodetectors. A combination of QDC-FETs, light emitting devise, photodetectors are vertically stacked to form a versatile 3-dimensional integrated circuit. Nonvolatile memories using floating quantum dot gates are included in vertical stacking format. Nonvolatile random access memories are integrated as a stack. Also described is the use of 3-layer stack of QDC-FETs making compact electrical circuits interfacing pixels for an active matrix flat panel displays that results in high resolution. Ge or Si quantum dot transport channel based devices processing spin polarized electrons introduced by magnetic tunnel junctions are described for multi-state coherent logic.

Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.

Abstract: A display device includes a substrate including a display region and non-display region, and at least one pixel disposed in the display region. The at least one pixel includes an emission region that emits a light, a non-emission region that does not emit the light, a light emitting element disposed in the emission region, and a pixel circuit that drives the light emitting element. The display device further includes a passivation layer disposed between the pixel circuit and the light emitting element. The passivation layer covers the pixel circuit and includes a concave pattern disposed in the non-emission region. The display device further includes a power supply line disposed on the passivation layer in the non-emission region and connected to the light emitting element. The power supply line includes an uneven pattern corresponding to the concave pattern.

Abstract: Illustrative systems and methods disclosed herein pertain to a circuit assembly having components mounted upon a substratum element. The components are encased in a conductive sheath that may be made of metal. The conductive sheath, which is operative as a heat sink and/or an EMI shield, is structurally constructed to counteract deformation of the substratum element when the one or more components heat up during operation, or due to ambient temperature changes. In one exemplary embodiment, the conductive sheath has different thickness at different locations. An edge portion located at a transition between a first thickness and a second thickness of the conductive sheath undergoes deformation that prevents warping of the circuit assembly due to heat. In another exemplary embodiment, the conductive sheath has a gap provided between adjacent segments. The gap allows room for thermal expansion and counteracts deformation of the circuit assembly caused by heating.

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

Abstract: A semiconductor device and a method of forming the semiconductor device are disclosed. A method includes forming a gate stack over a semiconductor structure. The gate stack is recessed to form a first recess. A first dielectric layer is formed along a bottom and sidewalls of the first recess, the first dielectric layer having a first etch rate. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a second etch rate, the first etch rate being higher than the second etch rate. A third dielectric layer is formed over the second dielectric layer. An etch rate of a portion of the third dielectric layer is altered. The first dielectric layer, the second dielectric layer, and the third dielectric layer are recessed to form a second recess. A capping layer is formed in the second recess.

Abstract: An array board 11b includes a display section AA, a source line 20 connected to the display section AA, a test circuit 40 connected to the source line 20 and configured to test the display section AA, a panel-side image input terminal that is disposed such that the test circuit 40 is between the terminal and the display section AA and to which a signal to be supplied to the source line 20 is input, a terminal connection line 51 connecting the source line 20 to the pane-side image input terminal 35A and the terminal connection line 51 including the terminal connection line 51 at least a part of which overlaps the test circuit 40 and a flattening film (insulation film) 28 at least disposed between an overlapping portion of the test circuit 40 and the terminal connection line 51.

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

Abstract: A light-emitting diode includes a light-emitting epitaxial laminated layer having a first surface and a second, opposing, surface, including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer; an omnidirectional reflector structure formed on the second surface of the light-emitting epitaxial laminated layer, including a transparent dielectric layer located on the second surface of the light-emitting epitaxial laminated layer and having conductive holes therein; a first transparent adhesive layer on one side surface of the transparent dielectric layer that is distal from the light-emitting epitaxial laminated layer; a second transparent adhesive layer on one side surface of the first transparent adhesive layer that is distal from the transparent dielectric layer; and a metal reflective layer on one side surface of the second transparent adhesive layer that is distal from the first transparent adhesive layer.

Abstract: An electronic device according to various embodiments of the present disclosure includes a housing, a printed circuit board located inside the housing, an electrical element mounted on the printed circuit board, and a shield can that covers the electrical element. A recess area is formed on at least a portion of the shield can, and a metal structure is mounted in the recess area to cool heat generated by the electrical element.