Abstract: A semiconductor device, which comprises an E-mode FET and a D-mode FET and utilizes a two-dimensional electron gas, comprises a semi-insulating semiconductor substrate, a channel layer, an electron-supply layer, a third layer, a first etching-stoppable layer, a fifth layer, and a second etching-stoppable layer, which layers are formed in sequence on the substrate. An etching process for forming grooves of gate electrodes of the FETs comprises a first etching treatment removing the first etching-stoppable layer portion in the E-mode FET region and the second etching-stoppable layer portion in the D-mode FET region, and a second etching treatment removing the third layer portion in the E-mode FET region and the fifth layer portion and using an etchant different from that used in the first etching treatment. In the second etching treatment, reactive ion etching method using a CCl.sub.2 F.sub.

Abstract: A method of making an (In,Ga)(As,P) inverted rib waveguide laser in which a lateral waveguiding effect is provided by an inverted rib formed in intermediate index material spacing the active layer from the substrate which accommodates the rib in a channel in the substrate includes forming the channel with {111}B or {011} plane side walls, thereby permitting the use of a thinner intermediate index material layer than is possible when using a channel with {111}A plane sides.

Abstract: The invention provides a unique VLSI dimensioned NPN type transistor and method of making the same, wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Spaced apart slots made in the substrate permit the introduction of orientation dependent etching fluid therein to at least substantially etch semi-arrays of active regions of the substrate away from the substrate except for spaced apart supports therealong. Oxidation serves to support the semi-arrays directly from the substrate or by webs of oxidation along the tops of the semi-arrays connected to the substrate.

Abstract: In a method of manufacturing a semiconductor device, a thin silicon dioxide (SiO.sub.2) film for a gate insulation film and a polycrystalline silicon layer are successively deposited on a semiconductor substrate having one electrical conductivity type whereby this polycrystalline silicon layer has a gate electrode pattern. In this step a part of the polycrystalline silicon layer is left at a part where an electric contact with the substrate is to be formed. Parts of source and drain regions are formed by the self-align method with this polycrystalline silicon layer as a mask. A thick passivation film for an interlayer insulation film is formed to cover the whole surface. An aperture is formed selectively in the passivation film to expose the whole polycrystalline silicon layer at the part where the contact is formed. The polycrystalline silicon layer in the aperture part and the thin insulation film thereunder are removed to expose a part of the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor device having a plurality of MOS transistors which construct a memory section. After forming a plurality of MOS transistors on a semiconductor substrate, source regions and drain regions of given MOS transistors are shorted in accordance with a requested program. An insulating film is subsequently formed on the MOS transistors and an interconnection wiring layer is further formed thereon.

Abstract: The reproducibility of Te doping in III-V group compounds is improved by using as the dopant a III-V group compound containing Te at a concentration of at least 1.times.10.sup.17 cm.sup.-3.

Abstract: A method of manufacture of a semiconductor device such as an MOS dynamic read/write memory cell array uses a doped multilevel oxide layer as a diffusion source to create source/drain regions and diffused interconnects. The process is thereby simplified since an ion implant ordinarily used for this purpose is avoided. The doped oxide subjected to a heat treatment for drive-in and densification, then is reflowed after contact holes are etched.

Abstract: A method for the manufacture of A.sub.3 B.sub.5 light-emitting diodes, particularly of light-emitting (Ga,Al)As diodes with Te and Zn as doping materials is provided. A first n-doped GaAlAs layer is epitaxially applied on a GaAs substrate from an n-doped (S,Se,Te) Ga,Al,As melt and after an interim precipitation without contact with the GaAs substrate, preferably on an auxiliary substrate, a GaAlAs layer p-doped with Zn or Mg is deposited on the substrate already epitaxially coated with the n-GaAlAs layer. Efficient light-emitting diodes are obtained.

Abstract: A method for trimming a diffused or implanted resistor located within an integrated circuit is disclosed. This technique for trimming a resistor requires the use of high current pulses and geometric shaped metal contacts. The current pulses react with the electropositive metal atoms in the thin film conductor and cause the metal atoms to migrate to another location, thus altering the value of the resistor by progressively decreasing the conductivity of the resistor.

Abstract: A process for forming a doped oxide film and a doped semiconductor suitable for electronic applications wherein a silicon tetraalkoxide is reacted with a limited amount of water to produce a low molecular weight, soluble polyorganosiloxane. The polyorganosiloxane is subsequently admixed with a soluble dopant element compound to form a homogeneous, polyorganosiloxane-dopant compound solution. The solution is coated onto a semiconductor wafer substrate material and heated to produce an impurity doped semiconductor wafer suitable for electronic application.

Abstract: In making a polysilicon resistor in a polycide line, a thick oxide is established selectively to shield lightly doped polysilicon first from heavy doping and then from the silicide. Before adding silicide, a selected region of polysilicon broader than and including the site of the poly resistor is exposed, lightly doped, and then oxidized to establish a thick oxide, while other areas are protected by nitride. Then the nitride and any thin oxide on top of the polysilicon outside the broad area are removed, and the exposed polysilicon is heavily doped for low resistivity. The thick oxide shields the underlying lightly doped polysilicon from the heavy doping. Silicide is then added. Definition of the polysilicon resistor follows preferably using a two step process. When the silicide is etched, the thick oxide on top of the broad polysilicon area acts as an etch stop. Then the thick oxide and polysilicon resistor are etched.

Abstract: Method of fabricating a monolithic integrated circuit structure incorporating a complementary pair of GaAs/AlGaAs modulation-doped field effect transistors (MODFET's) including providing a substrate of semi-insulating GaAs, depositing an epitaxial layer of undoped AlGaAs on its surface, and ion-implanting a heavily doped N-type donor region and a heavily doped P-type acceptor region in the undoped AlGaAs. A thin spacer layer of undoped AlGaAs is epitaxially deposited on the previously deposited AlGaAs layer, and an epitaxial layer of undoped GaAs is deposited on the spacer layer. First and second gate members which form Schottky barriers with the GaAs are placed on the GaAs layer overlying portions of the N-type donor region and P-type acceptor region, respectively. N-type source and drain zones are formed in the GaAs layer on opposite sides of the first gate member, and P-type source and drain zones are formed in the GaAs layer on opposite sides of the second gate member.

Abstract: A technique is described for doping a silicon body with boron. The surface to be doped is typically a trench sidewall, to be used as a storage capacitor or for isolation. By providing a silicon dioxide diffusion control layer, and a polysilicon source layer that incorporates the boron, well-controlled boron doping over a wide concentration range can be obtained. Control of the doping transfer can be obtained by the choice of ambients, either dry or steam. Furthermore, removal of the silicon dioxide and polysilicon layers following the doping process is facilitated due to the etch selectivity possible between SiO.sub.2 and Si. If desired, the layers may remain on the silicon body.

Abstract: A junction field effect transistor has a substrate forming a junction with a layer of semiconductor material which has a gate, a source and a drain therein. The thickness of the n-type layer underlying the source is substantially greater than that underlying the gate (for example the ratio of n-thickness below the gate to that below the source is 1 to 2.53) in order to reduce the parasitic resistance as compared to conventional JFETs.

Abstract: Double diffused power MOSFET's and methods of manufacture. The source, base and drain regions of a double diffused power MOSFET correspond respectively to the emitter, base and collector of a parasitic bipolar transistor. Double diffused power MOSFET's perform better when provided with an ohmic short between the source and base regions to prevent turn-on of the parasitic bipolar transistor. In one form of ohmic short between the base and source regions, the source terminal comprises a metallic electrode, preferably aluminum, deposited over the source region, and the ohmic short comprises at least one microalloy spike extending from the source terminal metallic electrode through the source region and partly into the base region. Such microalloy spikes are formed by heating the semiconductor substrate after the metallic electrode has been deposited under appropriate conditions. In another form, a V-groove is formed by preferential etching in the source and base regions.

Abstract: A structure having substantial surface evenness is created by a method in which an insulating layer (24) that has an upward protrusion (26) is formed on a patterned conductive layer (20) having a corresponding upward protrusion (22). A further layer (28) having a generally planar surface is formed on the insulating layer. Using an etchant that attacks the further layer much more than the insulating layer, the further layer is etched to expose at least part of the insulating protrusion. The further layer and the insulating layer (as it becomes exposed) are then etched with an etchant that attacks both of them at rates not substantially different from each other. This brings the upper surface down without exposing the conductive layer, particularly its upward protrusion.

Abstract: A liquid phase epitaxial growth method is disclosed wherein (111)A InP substrate is used for growing an epitaxial layer of Al.sub.x In.sub.1-x As or Al.sub.x Ga.sub.y In.sub.1-x-y As compound semiconductor by liquid phase epitaxy.

Abstract: A process for diffusing a dopant into a III-V type semiconductor body is disclosed which comprises:(a) placing in a heating chamber which is substantially devoid of any oxidizing substance a deposition substrate possessing a dopant-containing layer which has been vapor deposited upon a major surface thereof in contact with, or in the proximity of, an object substrate fabricated from a III-V type semiconductor material with the dopant-containing layer of the deposition substrate being substantially opposed to a major surface of the object substrate;(b) introducing into the heating chamber a source of Group V element corresponding to the Group V element of the object substrate, said source being capable of providing Group V element in the vapor phase at the diffusion temperature with the vapor pressure of the vapor phase Group V element being at or above the equilibrium vapor pressure of the Group V element present at the surface of the object substrate; and,(c) heating the deposition substrate and the object s

Abstract: A method of making infrared detectors on a substrate of mercury cadmium turide (HgCdTe) or mercury zinc telluride (HgZnTe). The steps include those of preparing the substrate, etching and passivating it, and placing it in the ultra-high vaccuum environment of a molecular beam epitaxy apparatus. While in the apparatus, one or more layers of zinc cadmium telluride (ZnCdTe) are deposited. When the ZnCdTe deposition is finished, the substrate is removed from the apparatus and the detectors are delineated lithographically.

Abstract: A method for fabricating junction field-effect transistors includes forming in an N-type silicon substrate a plurality of high-aspect-ratio bores interposed between a source region and a drain region in the substrate, diffusing P-type impurities a predetermined distance into the substrate from the inner surface to each bore to form a concentric, P-type gate zone around each bore, forming electrical contacts to the source and drain regions and to the gate zones and forming a P-type isolation zone surrounding the source and drain regions and the gate zones. The bores, which are preferably formed by laser drilling, extend completely or partially through the thickness of the substrate. The gate zones extend, either completely through the thickness of the substrate or from the top surface of the substrate to a layer-like P-type zone formed adjacent to the bottom surface thereof.