Abstract: A method for fabrication a vertical MOSFET which contains a protective element for protecting the gate electrode of an insulated gate field effect transistor. The protective element is formed of the same semiconductor layer as that of the gate electrode of the insulated gate field effect transistor and is formed integrally with the gate electrode on an insulating film formed on the surface of a semiconductor substrate.

Abstract: A method of manufacturing a semiconductor device having a single crystal pn junction formed in a Group II-VI compound semiconductor crystal, by: growing a Group II-VI compound semiconductor crystal substrate of n type from a melt of a crystal-constituting Group VI element other than Te; forming a crystal temperature difference in the melt which applying a vapor pressure of the Group VI element onto the melt; forming, on the substrate, a semiconductor region of p type by diffusing an acceptor impurity into the n type crystal under a predetermined vapor pressure of the constituent Group VI element. Thus, it becomes possible to provide light-emitting diodes emitting green, blue-green or violet color region if ZnSe crystals are used.

Abstract: A method of coding a ROM from a partially processed semiconductor wafer comprising a substrate, a plurality of spaced regions separated by regions of isolating oxide deposited in said substrate, a layer of gate oxide overlying each of said spaced regions and a gate electrode overlying each layer of said gate oxide, is described comprising the use of photoresist material for preventing the formation of source and drain regions under selected ones of said gate electrodes during a subsequent doping step. The photoresist material restricts the area of implantation of dopant used for forming source and drain regions in the ROM device.

Abstract: A method of manufacturing an electrolytic double-layer capacitor comprises steps of forming a laminated intermediate member in which an insulating gasket defines a central space containing a carbonaceous compact having a recess portion; and the insulating gasket is interposed between a separator, having a region provided with no liquid column of an electrolytic solution in a position corresponding to the recess portion, and a conductive sheet; and dripping the electrolytic solution from above the above mentioned region of the separator and then deforming the conductive sheet by negative pressure so as to cause the electrolytic solution to impregnate the compact.

Abstract: A method of making a floating gate memory cell wherein the capacitance between the control gate and floating gate can be independently controlled. Independent capacitance control is achieved by forming the inter-level dielectric in a step which is independent of the gate oxide growth process.

Abstract: Methods of doping Hg.sub.1-x Cd.sub.x Te (50) with fast diffusing dopants by immersion in a mercury reservoir (32) doped with the desired dopants are disclosed. Also, methods of core annihilation of Hg.sub.1-x Cd.sub.x Te slices or ingots by immersion in a heated mercury reservoir are disclosed. Preferred embodiments include dopants such as copper in a mercury reservoir (32) that is heated to 270.degree. C. for a Hg.sub.1-x Cd.sub.x Te slice, and a reservoir (32) that is heated to 150.degree. C. for a thin film of Hg.sub.1-x Cd.sub.xn Te on a CdTe substrate.

Abstract: A transistor is provided which includes an electrical contact (122) formed in a V-shaped groove (118). Because of the unique shape of the electrical contact, a smaller surface area is required for its formation thus rendering it possible to construct a transistor having a smaller surface area. The groove is formed by anisotropically etching an expitaxial layer (102) on a semiconductor substrate (100) using, for example, KOH.

Abstract: A high power MOSFET structure consists of a plurality of source cells distributed over the upper surface of a semiconductor chip, with a drain electrode on the bottom of the chip. Each of the source cells is hexagonal in configuration and is surrounded by a narrow, hexagonal conduction region disposed beneath a gate oxide. The semiconductor material beneath the gate oxide has a relatively high conductivity, with the carriers being laterally equally distributed in density beneath the gate oxide. The high conductivity hexagonal channel is formed in a low conductivity epitaxially formed region and consists of carriers deposited on the epitaxial region prior to the formation of the source region. Symmetrically arranged gate fingers extend over the upper surface of the device and extend through and along slits in the upper source metallizing and are connected to a polysilicon gate grid which overlies the gate oxide.

Abstract: A process of fabricating a semiconductor device, wherein a semiconductor substrate of one conductivity type has formed therein layers including a semiconductor layer of the opposite conductivity type, an anti-oxidation mask layer, a doped polysilicon layer, an anti-etch mask layer and a silicon oxide film. Within the substrate are defined isolation areas, from which the silicon oxide film, anti-etch mask layer and doped polysilicon layer are selectively etched away. On the resultant structure is formed an undoped or lightly doped polysilicon layer. Then, the structure is heated to cause atoms of the impurity in the doped polysilicon layer to diffuse into the directly adjacent portions of the undoped or lightly doped polysilicon layer. The undoped or lightly doped polysilicon layer is then etched away over its areas on the silicon oxide film and on the device isolation areas of the substrate. The anti-oxidation mask layer is partially etched away.

Abstract: A high-density MOSFET having field oxide self-aligned channel stops for device isolation and an optimal method of fabricating such a device is described. The process provides channel stops underlying and aligned with the edges of a field oxide layer and allows the dopant concentration of the channel stops to be established separately from that of the active device channel region by use of an independant channel stop implant. The active devices thus formed require minimal isolation area, have a high field threshold voltage, a low junction capacitance, and minimal body effect. They are particularly useful in high-speed, high-performance integrated circuits.

Abstract: The disclosure relates to a method for realizing a fully functional buried level of interconnect using only a single level of a silicide over N+ polycrystalline silicon, the latter serving as the gate material for both the N channel and P channel devices formed.

Abstract: A technique is described for doping a silicon body with boron. The surface to be doped is typically a trench sidewall, to be used as a storage capacitor or for isolation. By providing a silicon dioxide diffusion control layer, and a polysilicon source layer that incorporates the boron, well-controlled boron doping over a wide concentration range can be obtained. Control of the doping transfer can be obtained by the choice of ambients, either dry or steam. Furthermore, removal of the silicon dioxide and polysilicon layers following the doping process is facilitated due to the etch selectivity possible between SiO.sub.2 and Si. If desired, the layers may remain on the silicon body.

Abstract: A method of manufacturing an LED including a substrate with an elevated surface portion, an epitaxial blocking layer adjacent thereto, and a double-heterojunction structure thereover.

Abstract: The present invention provides an improved method of forming semiconductor fuses involving the use of silicide formation by a low temperature process which avoids heat related damage to other device components and circuitry and which provides better electrical reliability than fuses formed by alternative porcesses. According to the present invention, silicides of noble and refractory metals can be formed by solid phase diffusion to form vertical fuses which are conductive after silicide formation.

Abstract: The method of controlling the modeling of the well energy band profile by interdiffusion comprises at least one thin disordering component layer contiguous with a surface of the quantum well layer and including a high content of a disordering component therein compared to the level of content thereof in semiconductor layers immediately adjacent thereto. The disordering components are Al and Ga in the GaAs/GaAlAs regime.

Abstract: A method for forming a diffused region on a semiconductor substrate is provided. A silicide layer is formed in a region of a substrate where a diffused layer is to be formed and a material containing an impurity to be defined into the substrate deposited on the silicide layer. The device is heat treated to cause the impurity to diffuse through the silicide layer into the substrate. The method may be used to produce a MOSFET.

Abstract: A semiconductor device having an uneven distribution of impurity concentration is manufactured easily and with good reproducibility from a wafer of a Group III-V or Group II-VI compound semiconductor by first forming a thin layer of impurity in a desired region of a principal surface of the wafer by, for example, an ion-implantation technique, and then subjecting the wafer to heat treatment under a controlled vapor pressure of at least one of the component elements of the compound semiconductor in order to maintain the stoichiometric composition of the impurity layer.

Abstract: The present invention relates to a Bi-CMOS.

Abstract: A self-aligned gate process for integrated circuits based on modulation doped (Al, Ga)As/GaAs field effect transistors and in which the regions on each side of the metal silicide gate are heavily ion implanted to form the low resistance regions on either side of the gate.

Abstract: A method of producing a gate turn-off thyristor includes producing a first n type impurity region, a second p type impurity region, a third n type impurity region, and a fourth p type impurity region produced in a semiconductor substrate providing a cathode electrode in contact with the first n type impurity region, providing a gate electrode in contact with the second p type impurity region, and an anode electrode which short-circuits the third and the fourth regions at the second main surface of the semiconductor substrate. Gold is diffused into the third region at a predetermined diffusion temperature thereby shortening the life time of carriers in the substrate.