Abstract: Herein disclosed is a process for fabricating a semiconductor integrated circuit device which is provided with N-channel and P-channel MISFETs each having a pair of side wall spacers formed simultaneously at both the sides of a gate electrode thereof. The P-channel MISFET has its source and drain regions formed by a boron ion implantation using the gate electrode and the paired side wall spacers as a mask. The boron having a high diffusion velocity is suppressed from diffusing below the gate electrode.

Abstract: A method of manufacturing a GaAs semiconductor device of an E/D construction having a GaAs/AlGaAs heterojunction and utilizing two-dimensional electron gas, which includes the steps of forming a heterojunction semiconductor substrate and etching a portion of the substrate to provide a gate portion of a depletion-mode FET. When the substrate of a semi-insulating GaAs layer, an undoped GaAs, an N-type AlGaAs layer providing an electron-supply layer, and a GaAs layer is formed, the GaAs layer is composed of a first GaAs layer, an etching stoppable AlGaAs layer, and a second GaAs layer, the first GaAs layer being formed on the N-type GaAs layer. The etching for provision of the gate portion is carried out by a dry etching method using an etchant of CCl.sub.2 F.sub.2 gas, so that the second GaAs layer can be etched but the AlGaAs layer cannot be etched.

Abstract: Proposed is a method of fabricating III-V and II-VI compound semiconductors and a resulting product where there is formed on the surface a coating which can function as a diffusion mask and/or a passivation layer. The coating is a silicon layer deposited by a method which does not damage the semiconductor surface.

Abstract: A process for the production of semiconductor devices includes: (1) forming a thin semiconductor film containing no aluminum on a first semiconductor layer containing aluminum that is disposed on a substrate one or more (2) forming channels on said thin semiconductor film in such a manner that the channel or channels reach or go through said first semiconductor layer to expose a portion of said substrate, resulting in a channelled substrate for succeeding crystal growth thereon, and (3) producing by epitaxial growth crystalline layers on said channelled substrate by the use of a crystal growth solution having a supersaturation which is high enough to prevent said first semiconductor layer from undergoing meltback.

Abstract: Increased barrier heights at metal(36)-semiconductor(32) contacts for semiconductors such as gallium arsenide by formation of an opposite doping type thin layer (34) on the semiconductor (32) surface by surface diffusion of dopants are disclosed. Preferred embodiments diffuse zinc 50 to 400 .ANG. into n type gallium arsenide (32) by rapid thermal pulses; then aluminum or titanium-platinum (36) contacts to the zinc doped layer (34) are deposited by evaporation and lift off.

Abstract: An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.

Abstract: A method of manufacturing a semiconductor device, in which an epitaxial layer doped with magnesium compounds of elements from the groups III and V of the periodic system of elements is deposited on a surface of a semiconductor body. For this purpose, the semiconductor body is brought into contact with a saturated solution of the compound, in which magnesium is present. Magnesium is added to the solution in the form of magnesium silicide, magnesium germanide or magnesium stannide. Thus, the epitaxial layer can be doped in a very reproducible manner, while moreover defects in the layer due to magnesium oxide particles are prevented.

Abstract: A method of forming a shallow n-type region of a semiconductor device, such as a bipolar transistor or a MOS FET, includes the following steps. Forming a first film containing arsenic or antimony on a silicon substrate; forming a second film containing phosphorus on the first film; and diffusing the arsenic or antimony and the phosphorus into the semiconductor substrate out of the first and second films by heat-treatment. The diffused impurities of the arsenic or antimony and the phosphorus form the n-type region and the arsenic or antimony defines the depth of the n-type region.

Abstract: In stacked CMOS, a single gate in first level polysilicon is used to address both an n-channel device in the substrate and an overlayed p-channel device. To self-align the p-channel polycrystalline silicon device to the gate, a layer of polycrystalline silicon is deposited over the integrated circuit, followed by spinning on a layer of doped oxide which is then etched back to expose the polycrystalline silicon over the gate region. Thermally annealing the integrated circuit causes dopant from the doped layer to diffuse into the polycrystalline layer, thereby forming self-aligned source and drain structures.

Abstract: Method of producing a silicon structure for fabricating integrated circuit devices therein by forming a plurality of regions of N-type single crystal silicon of high resistivity inset in the surface of silicon of either P-type conductivity or of N-type conductivity of low resistivity. The silicon contiguous with the regions of high resistivity N-type silicon is converted to porous silicon by anodically treating in an aqueous solution of HF. Then, conductivity type imparting material is diffused through the porous silicon into portions of the regions of N-type conductivity to alter their electrical characteristics to P-type or to low resistivity N-type. The porous silicon is then oxidized to silicon oxide, electrically isolating each of the N-type regions and its associated portion.

Abstract: Gate current leakage is reduced in a submicron FET device by the deposition of an oxide layer over the gate prior to the rapid heating of the device. This is done to prevent the dopant that was implanted into the gate from collecting on the sidewalls of the gate and the oxide layer between gate and substrate. Otherwise the diffused dopant becomes the path of least resistance, thus creating current leakage from the gate to source or gate to drain.

Abstract: A manufacturing method of a semiconductor device is disclosed which includes the steps of forming oxide layers on a major surface of a substrate at first and second portions, forming first and second semiconductor layers, each having predetermined conductivity types and with predetermined patterns on the oxide layers of the first and second portions, forming a first region by introducing an impurity of the first conductivity type into the substrate while using the first semiconductor layer as a mask, etching out the oxide layer on the second portion by using the second semiconductor layer as a mask, forming a second region by introducing an impurity of the second conductivity type into the substrate while using the second semiconductor layer as a mask, and forming oxide layers on the surfaces of the first semiconductor layer, the second semiconductor layer and the second region by a thermal oxidization process.

Abstract: A method for forming a CMOS FET structure includes the steps of forming an apertured insulating layer on a silicon substrate and epitaxially forming a monocrystalline silicon island of first conductivity type through an aperture therein. The exposed surface of the silicon island is then thermally oxidized and the portion of the insulating layer not covered by the oxide is removed. A monocrystalline silicon island of second conductivity type is then formed adjacent to the oxidized silicon island of first conductivity type.

Abstract: A method of manufacturing a semiconductor device by the use of a Group II-VI compound semiconductor crystal prepared by liquid growth method using a temperature difference technique under controlled vapor pressure of the crystal-constituting Group VI element. Thus, the concentration of vacancies and other defects acting as donor is reduced as compared with the concentration of the p type impurity to be introduced. This invention is suitable for producing light-emitting diodes emitting a light of short-wave lengths.

Abstract: A method of manufacturing a semiconductor device is disclosed. In the manufacturing method, an impurity diffusion layer as a first interconnection layer is formed on a semiconductor substrate. Then, an aluminum layer as a second interconnection layer is formed on the semiconductor substrate with an insulating film interposing therebetween. Another insulating layer is further formed on the aluminum layer. An anisotropic etching process is applied to the insulating layer, the second interconnection layer, and the insulating film, thereby forming a contact extending up to the first interconnection layer through these layers, and the insulating film. After the formation of the contact hole, an aluminum layer is formed on the entire surface of the insulating film including the inner surface of the contact hole. The aluminum layer formed in the contact hole electrically interconnects the first and second interconnecting layers.

Abstract: A process for forming a doped oxide film suitable for doping a semiconductor wafer substrate material and composite article. A silicon tetra-alkoxide is reacted with a limited amount of water to produce a low molecular weight, soluble polyorganosiloxane. The polyorganosiloxane is subsequently admixed with a reactive dopant source to form a soluble metallosiloxane polymer. The metallosiloxane polymer is coated onto a semiconductor wafer substrate material to produce a metallosiloxane-wafer composite article. The composite article is heated to produce an impurity doped semiconductor wafer suitable for electronic applications.

Abstract: A process for fabricating an X-ray spectrometer having imaging and energy resolution of X-ray sources. The spectrometer has an array of adjoining rectangularly shaped detector cells formed in a silicon body. The walls of the cells are created by laser drilling holes completely through the silicon body and diffusing n.sup.+ phosphorous doping material therethrough. A thermally migrated aluminum electrode is formed centrally through each of the cells.

Abstract: The two transistors of a bipolar flip-flop structure are interconnected by using a polycrystalline silicon/metal silicide sandwich structure. The polycrystalline silicon is doped to correspond to the underlying regions of the transistor structures, and undesired PN junctions created thereby are eliminated by depositing refractory metal silicide on the upper surface of the polycrystalline silicon.

Abstract: Using a process constructed in accordance with the teachings of this invention, a double recess, N+ ledge field effect transistor may be formed using a single masking step. Two layers of photoresist of differing types are formed on the surface of an N+ epitaxial layer. On the surface of these photoresist layers a layer of material which may be etched by reactive ion etching with freon but will not etch by reactive ion etching with oxygen is formed. A gate pattern is etched into this surface layer of material and the photoresist layers are selectively undercut to provide a pattern to etch the gate recess and the wide recess. A gate contact is then formed by perpendicular evaporation through the gate pattern in the surface layer of material. Thus the invention provides a process for forming a self-aligned double recess transistor using a single mask to form the gate, the wide recess and the gate recess, and another mask to form the source and drain contacts.

Abstract: A method of fabricating a MOS device is disclosed, in which, after formation of a gate electrode and source, drain regions, conductive material films are formed by selective CVD on the exposed surfaces of the gate electrode and source, drain regions. The conditions of the selective CVD are set such that the conductive material films formed on the source and drain regions partly overlay over the field insulating film adjacent to and surrounding the source and drain regions.