Patents Examined by Grant S Withers
  • Patent number: 11373995
    Abstract: A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising III-N material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure, an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11367615
    Abstract: A method of fabricating transistors with short gate length by two-step photolithography is provided. This method utilizes the two-step photolithography by a stepper as well as controlling a first exposed position and a second exposed position to change the gate length.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: June 21, 2022
    Assignee: National Chiao Tung University
    Inventors: Yi Chang, Yueh-Chin Lin, Po-Sheng Chang
  • Patent number: 11362206
    Abstract: A nitride semiconductor device includes: a substrate having a first main surface and a second main surface; a first nitride semiconductor layer of a first conductivity type provided above the first main surface; a second nitride semiconductor layer of a second conductivity type provided above the first nitride semiconductor layer; a first opening which penetrates through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer provided above the second nitride semiconductor layer and on an inner surface of the first opening; a gate electrode provided above the electron transport layer and covering the first opening; a source electrode connected to the second nitride semiconductor layer; a drain electrode provided on a second main surface-side of the substrate; and a high-resistance layer provided between the second nitride semiconductor layer and the electron transport layer in the first opening, the high-resistance layer including a nitride semiconductor.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: June 14, 2022
    Assignee: PANASONIC CORPORATION
    Inventors: Masahiro Ogawa, Daisuke Shibata, Satoshi Tamura
  • Patent number: 11355527
    Abstract: A display panel and a preparation method thereof, and a display device are disclosed. The display panel includes a display region and a bending region located outside the display region. The display panel includes a source-and-drain electrode metal layer. The display panel includes an organic photoresist layer in the bending region. A bending-region interlayer dielectric layer is disposed at one side of the organic photoresist layer near the source-and-drain electrode metal layer. Source-and-drain electrode traces can be prevented from breaking.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: June 7, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Ding Ding
  • Patent number: 11349012
    Abstract: In an embodiment, a Group III nitride-based transistor device, includes a first. Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first. Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length ld, and 0 nm?ld?200 nm.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: May 31, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Ostermaier, Oliver Haeberlen, Gerhard Prechtl, Manuel Stabentheiner
  • Patent number: 11335627
    Abstract: A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: May 17, 2022
    Assignee: Silanna Asia Pte Ltd
    Inventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
  • Patent number: 11335801
    Abstract: A device including a III-N material is described. In an example, a device includes a first layer including a first group III-nitride (III-N) material and a polarization charge inducing layer, including a second III-N material, above the first layer. The device further includes a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The source structure and the drain structure both include a first portion adjacent to the first layer and a second portion above the first portion, the first portion includes a third III-N material with an impurity dopant, and the second portion includes a fourth III-N material, where the fourth III-N material includes the impurity dopant and further includes indium, where the indium content increases with distance from the first portion.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta
  • Patent number: 11322599
    Abstract: A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous Al1-xSixO layer with 0.2<x<0.8; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: May 3, 2022
    Assignee: Transphorm Technology, Inc.
    Inventors: Carl Joseph Neufeld, Mo Wu, Toshihide Kikkawa, Umesh Mishra, Xiang Liu, David Michael Rhodes, John Kirk Gritters, Rakesh K. Lal
  • Patent number: 11315864
    Abstract: A package structure of a common-source common-gate gallium nitride field-effect transistor is disclosed, including a lead frame. A gallium nitride field-effect transistor and a metal oxide semiconductor are directly disposed on the lead frame. The gallium nitride field-effect transistor includes a first matrix directly disposed on the lead frame. A first drain, a first gate, and a first source are disposed on a surface side of the first matrix, and the first drain and the first gate are separately electrically connected to the lead frame. The metal oxide semiconductor includes a second matrix directly disposed on the lead frame. A second drain, a second gate, and a second source are disposed on a surface side of the second matrix, the second drain is directly electrically connected to the first source, and the second gate and the second source are separately electrically connected to the lead frame.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: April 26, 2022
    Assignee: GAN POWER TECHNOLOGY CO., LTD.
    Inventors: Tsung Hsien Yen, Hsing Yeh Wang, Feng Jui Shen
  • Patent number: 11316038
    Abstract: An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: April 26, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Ferdinando Iucolano
  • Patent number: 11315835
    Abstract: One illustrative method disclosed herein includes forming a conformal SMCM layer above a conformal high-k gate insulation layer within each of first and second replacement gate cavities (RGC), removing the SMCM layer from the first RGC while leaving the SMCM layer in position within the second RGC, forming a first conformal metal-containing material (MCM) layer above the gate insulation layer within the first RGC and above the SMCM layer in position within the second RGC, removing the first conformal MCM layer and the conformal SMCM layer positioned within the second RGC while leaving the first conformal MCM layer within the first RGC, and forming a second conformal MCM layer above the first conformal MCM layer positioned within the first RGC and above the gate insulation layer positioned within the second RGC.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 26, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Wei Hong, Hong Yu, Tao Chu, Bingwu Liu
  • Patent number: 11316041
    Abstract: A semiconductor device (1) includes a substrate (2), an electron transit layer (4) disposed on the substrate (2), and an electron supply layer (5) disposed on the electron supply layer (4). The electron transit layer (4) includes a conductive path forming layer (43) in contact with the electron supply layer (5), a first semiconductor region (first nitride semiconductor layer) (41) containing an acceptor-type impurity, and a second semiconductor region (second nitride semiconductor layer) (42) disposed at a position closer to the conductive path forming layer (43) than the first semiconductor region (41) and containing an acceptor-type impurity. The first semiconductor region (41) has a higher acceptor density than the second semiconductor region (42).
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 26, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Taketoshi Tanaka
  • Patent number: 11309360
    Abstract: A color conversion substrate includes a base on which first to third light outputting regions and a light shielding region surrounding the first to third light outputting regions are defined; first to third color filters on the base in the first to third light outputting regions, respectively; a first light shielding member on the first color filter in the light shielding region; a light transmission pattern on the first color filter; a first wavelength conversion pattern on the second color filter and which converts light of a first color into light of a second color; and a second wavelength conversion pattern on the third color filter and which converts the light of the first color into light of a third color. A first opening located in the light shielding region is defined in at least one of the light transmission pattern and the first and second wavelength conversion patterns.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sun Kyu Joo, Byung Chul Kim, In Ok Kim, Jae Min Seong, In Seok Song, Keun Chan Oh, Gak Seok Lee, Ji Eun Jang, Chang Soon Jang
  • Patent number: 11302690
    Abstract: The present invention provides a nitride semiconductor device capable of forming a half-bridge circuit and suppressing changes in current collapse characteristics. A first transistor of the present invention includes a first nitride semiconductor layer, and a first gate electrode, a first source electrode and a first drain electrode formed thereon. The second transistor includes a second nitride semiconductor layer, and a second gate electrode, a second source electrode and a second drain electrode formed thereon. The source electrode is electrically connected to a lower region of a first region on the substrate, the second source electrode is electrically connected to a lower region of a second region on the substrate, and a first insulating region is disposed between a portion corresponding to the first region on the substrate and a portion corresponding to the second region on the substrate.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: April 12, 2022
    Assignee: ROHM Co., Ltd.
    Inventor: Hirotaka Otake
  • Patent number: 11302788
    Abstract: A semiconductor device, comprising: a semiconductor substrate; a source, a gate and a drain fabricated on one side of the semiconductor substrate; a via hole region reserved in the region of the source; and an etching stopping layer made in the via hole region as well as a via hole under the etching stopping layer penetrating through the semiconductor substrate.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: April 12, 2022
    Assignee: Dynax Semiconductor Inc.
    Inventors: Pan Pan, Naiqian Zhang, Xi Song, Jianhua Xu
  • Patent number: 11289594
    Abstract: A GaN-based superjunction vertical power transistor and a manufacturing method thereof. The transistor includes: a N?-GaN layer; a first P-GaN layer as a current blocking layer, formed on the N?-GaN layer and having a gate region window; and a thin barrier Al(In, Ga)N/GaN heterostructure conformally formed on the current blocking layer and filling the bottom and one or more sidewalls of the gate region window, wherein the N?-GaN layer has an etched groove completely or partially filled with a second P-type GaN layer, an N+-GaN layer is formed under the second P-type GaN layer, and the N+-GaN layer is in direct contact with the second P-type GaN layer and the N?-GaN layer to form a superjunction composite structure.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 29, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Sen Huang, Xinhua Wang, Xinyu Liu, Yuankun Wang, Haibo Yin, Ke Wei
  • Patent number: 11264569
    Abstract: A phase change material memory device is provided. The phase change material memory device includes one or more electrical contacts in a substrate, and a dielectric cover layer on the electrical contacts and substrate. The phase change material memory device further includes a lower conductive shell in a trench above one of the one or more electrical contacts, and an upper conductive shell on the lower conductive shell in the trench. The phase change material memory device further includes a conductive plug filling the upper conductive shell. The phase change material memory device further includes a liner layer on the dielectric cover layer and conductive plug, and a phase change material block on the liner layer on the dielectric cover layer and in the trench.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Injo Ok, Kevin W. Brew, Timothy M. Philip, Muthumanickam Sankarapandian, Sanjay C. Mehta, Nicole Saulnier, Steven M. Mcdermott
  • Patent number: 11257939
    Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, in which the buffer layer includes a first buffer layer and a second buffer layer. Preferably, the first buffer layer includes a first layer of the first buffer layer comprising AlyGa1-yN on the substrate and a second layer of the first buffer layer comprising AlxGa1-xN on the first layer of the first buffer layer. The second buffer layer includes a first layer of the second buffer layer comprising AlwGa1-wN on the first buffer layer and a second layer of the second buffer layer comprising AlzGa1-zN on the first layer of the second buffer layer, in which x>z>y>w.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: February 22, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Yu-Chi Wang, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11258010
    Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) such as in a CEM device capable of switching between and/or among impedance states. In particular embodiments, a CEM may be formed from one or more transition metal oxides (TMOs), one or more post transition metal oxides (PTMOs) or one or more post transition metal chalcogenides (PTMCs), or a combination thereof.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: February 22, 2022
    Assignee: Cerfe Labs, Inc.
    Inventors: Carlos Alberto Paz de Araujo, Saurabh Vinayak Suryavanshi, Lucian Shifren, Jolanta Bozena Celinska
  • Patent number: 11257918
    Abstract: A semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; an ohmic electrode above the substrate; and a contact layer in contact with at least a part of the ohmic electrode, the contact layer containing silicon and chlorine. The second nitride semiconductor layer has a wider band gap than the first nitride semiconductor layer. A two-dimensional electron gas channel is formed in the first nitride semiconductor layer at a heterointerface between the first nitride semiconductor layer and the second nitride semiconductor layer. A silicon concentration has a higher peak value than a chlorine concentration in the contact layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 22, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Kanda, Hideyuki Okita, Manabu Yanagihara, Takeshi Harada