Patents Examined by Grant S Withers
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Patent number: 12230701Abstract: A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.Type: GrantFiled: January 20, 2023Date of Patent: February 18, 2025Assignee: MACOM Technology Solutions Holdings, Inc.Inventors: Khaled Fayed, Simon Wood
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Patent number: 12224220Abstract: A semiconductor module includes a first power semiconductor device, a conductive wire, and a resin film. The conductive wire is joined to a surface of a first front electrode of the first power semiconductor device. The resin film is formed to be continuous on at least one of an end portion or an end portion of a first joint between the first front electrode and the conductive wire in a longitudinal direction of the conductive wire, a surface of the first front electrode, and a surface of the conductive wire. The resin film has an elastic elongation rate of 4.5% to 10.0%.Type: GrantFiled: February 6, 2020Date of Patent: February 11, 2025Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Ken Sakamoto, Haruko Hitomi, Kozo Harada, Seiki Hiramatsu
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Patent number: 12224331Abstract: A semiconductor device includes: a gate electrode including a junction portion forming a Schottky junction with a barrier layer; a projecting portion including first and second gate field plates and projecting from the junction portion; and an insulating layer including first and second sidewalls. An angle formed between a highest position of a bottom surface of the first gate field plate and a main surface of a substrate, viewed from the first position, is a second elevation angle. An angle formed between an end on the drain electrode side of a lowest portion of a bottom surface of the second gate field plate and the main surface, viewed from the first position, is a third elevation angle. The second elevation angle is larger than the third elevation angle. The bottom surface of the second gate field plate includes an inclined surface where a distance from the barrier layer monotonically increases.Type: GrantFiled: September 25, 2024Date of Patent: February 11, 2025Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Katsuhiko Kawashima, Yoshinori Takami, Dai Motojima, Yusuke Kanda
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Patent number: 12218294Abstract: A light source device includes: a mounting board; a plurality of light-emitting parts disposed on the mounting board, each of the plurality of light-emitting parts being configured to be individually turned on; a light-shielding member defining an opening; and a light-guide member supported by the light-shielding member, the light-guide member comprising a Fresnel lens portion, wherein, in a top view, the Fresnel lens portion is located within an area of the opening of the light-shielding member. In the top view, irradiation areas of the respective light-emitting parts are at least partially separated from each other.Type: GrantFiled: September 2, 2022Date of Patent: February 4, 2025Assignee: NICHIA CORPORATIONInventors: Tsuyoshi Okahisa, Norimasa Yoshida
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Patent number: 12218233Abstract: A high electron mobility transistor and a method of manufacturing the same are disclosed. The high electron mobility transistor includes a channel layer, a channel supplying layer causing generation of a two-dimensional electron gas (2DEG) in the channel layer, a source electrode and a drain electrode provided on respective sides of the channel supplying layer, a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG, a gate electrode provided on a portion of the depletion forming layer, and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer. The current limiting layer limits a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.Type: GrantFiled: September 2, 2022Date of Patent: February 4, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Jaejoon Oh, Jongseob Kim
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Patent number: 12218282Abstract: A light-emitting device includes a first semiconductor layer; a semiconductor pillar formed on the first semiconductor layer, including a second semiconductor layer and an active layer, wherein the semiconductor pillar comprises an outmost periphery; a first contact layer formed on the first semiconductor layer and including a first contact portion and a first extending portion, wherein the first extending portion continuously surrounds an entirety of the outmost periphery of the semiconductor pillar and the first contact portion; a second contact layer formed on the second semiconductor layer; a first insulating layer including multiple first openings exposing the first contact layer and multiple second openings exposing the second contact layer; a first electrode contact layer connected to the first contact portion through the multiple first openings and covering all of the first contact layer; a second electrode contact layer connected to the second contact layer through the multiple second openings.Type: GrantFiled: December 29, 2022Date of Patent: February 4, 2025Assignee: EPISTAR CORPORATIONInventors: Aurelien Gauthier-Brun, Chao-Hsing Chen, Chang-Tai Hsaio, Chih-Hao Chen, Chi-Shiang Hsu, Jia-Kuen Wang, Yung-Hsiang Lin
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Patent number: 12218279Abstract: An optoelectronic device includes a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; a first insulating layer on the second semiconductor layer and including a plurality of first openings exposing the first semiconductor layer, wherein the first openings include a first group and a second group; a third electrode on the first insulating layer and including a first extended portion and a second extended portion, wherein the first extended portion and the second extended portion are respectively electrically connected to the first semiconductor layer through the first group of the first openings and the second group of the first openings, and wherein the number of the first group of the first openings is different from the number of the second group of the first openings; and a plurality of fourth electrodes on the second insulating layer and electrically connected to the second semiconductor layer, wherein in aType: GrantFiled: January 11, 2024Date of Patent: February 4, 2025Assignee: EPISTAR CORPORATIONInventors: Chao-Hsing Chen, Jia-Kuen Wang, Chien-Chih Liao, Tzu-Yao Tseng, Tsun-Kai Ko, Chien-Fu Shen
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Patent number: 12218231Abstract: An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.Type: GrantFiled: December 9, 2020Date of Patent: February 4, 2025Assignee: STMicroelectronics S.r.l.Inventors: Ferdinando Iucolano, Alessandro Chini
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Patent number: 12211839Abstract: The present invention provides a nitride semiconductor device, including: a silicon substrate; a first lateral transistor over a first region of the silicon substrate and including: a first nitride semiconductor layer formed over the silicon substrate; and a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer; a second lateral transistor over a second region of the silicon substrate and including: a second nitride semiconductor layer formed over the silicon substrate; and a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer; a first separation trench formed over a third region; a source/substrate connecting via hole formed over the third region; a first interlayer insulating layer formed over the first source electrode and the second source electrode; and a second interlayer insulating layer formed in the first separation trench.Type: GrantFiled: December 21, 2023Date of Patent: January 28, 2025Assignee: ROHM CO., LTD.Inventor: Hirotaka Otake
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Patent number: 12213319Abstract: There is provided a semiconductor memory device including: a substrate having a Complementary Metal Oxide Semiconductor (CMOS) circuit; a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on the substrate; a channel structure having a first part penetrating the gate stack structure and a second part extending from one end of the first part, the second part extending beyond the gate stack structure; a common source line extending to overlap with the gate stack structure, the common source line surrounding the second part of the channel structure; a memory layer disposed between the first part of the channel structure and the gate stack structure; and a bit line connected to the other end of the first part of the channel structure, the bit line being disposed between the substrate and the gate stack structure.Type: GrantFiled: September 1, 2022Date of Patent: January 28, 2025Assignee: SK hynix Inc.Inventor: Nam Jae Lee
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Patent number: 12205987Abstract: A wafer includes a substrate and at least one intermediate layer formed on a surface of the substrate. The at least one intermediate layer covers the surface of the substrate at least partially. An outer surface of the at least one intermediate layer is directed away from the surface of the substrate. The wafer further includes nanostructures grown on the outer surface of the at least one intermediate layer. The at least one intermediate layer is formed in such a way that positions of growth of the nanostructures are predetermined on the outer surface of the at least one intermediate layer. At least one nanostructure material of the nanostructures is assembled at the positions of growth of the nanostructures.Type: GrantFiled: May 28, 2020Date of Patent: January 21, 2025Assignee: Technische Universität MünchenInventors: Christian Dangel, Jonathan Finley, Kai Müller, Frederik Bopp, Arne Ludwig, Nikolai Bart, Andreas Wieck
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Patent number: 12198934Abstract: A multilayer semiconductor structure of the present disclosure includes a substrate a buffer layer disposed on the substrate and a semiconductor layer disposed on the buffer layer. A void is provided between the buffer layer and the semiconductor layer.Type: GrantFiled: March 18, 2022Date of Patent: January 14, 2025Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Takahide Hirasaki
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Patent number: 12199028Abstract: A semiconductor device 1 has an electrode structure that includes source electrodes 3, a gate electrode 4, and drain electrodes 5 disposed on a semiconductor laminated structure 2 and extending in parallel to each other and in a predetermined first direction and a wiring structure that includes source wirings 9, drain wirings 10, and gate wirings 11 disposed on the electrode structure and extending in parallel to each other and in a second direction orthogonal to the first direction. The source wirings 9, the drain wirings 10, and the gate wirings 11 are electrically connected to the source electrodes 3, the drain electrodes 5, and the gate electrode 4, respectively. The semiconductor device 1 includes a conductive film 8 disposed between the gate electrode 4 and the drain wirings 10 and being electrically connected to the source electrodes 3.Type: GrantFiled: May 16, 2023Date of Patent: January 14, 2025Assignee: ROHM CO., LTD.Inventors: Minoru Akutsu, Kentaro Chikamatsu
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Patent number: 12191295Abstract: An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a host wafer, and the chiplets have interconnections to host wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The host wafer has at least one host wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The host wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the host wafer circuit to the chiplet circuit.Type: GrantFiled: June 25, 2024Date of Patent: January 7, 2025Assignee: PseudolithIC, Inc.Inventors: James F. Buckwalter, Florian Herrault, Justin Kim, Michael Hodge, Daniel S. Green
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Patent number: 12183676Abstract: In order to reduce costs as well as to effectively dissipate heat in certain RF circuits, a semiconductor device of the circuit can include one or more active devices such as transistors, diodes, and/or varactors formed of a first semiconductor material system integrated onto (e.g., bonded to) a base substrate formed of a second semiconductor material system that includes other circuit components. The first semiconductor material system can, for example, be the III-V or III-N semiconductor system, and the second semiconductor material system can, for example be silicon.Type: GrantFiled: January 13, 2023Date of Patent: December 31, 2024Assignee: MONDE WIRELESS INCInventors: Brian Romanczyk, Matthew Guidry
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Patent number: 12183815Abstract: High Electron Mobility Transistors (HEMTs) are described with a circular gate, with a drain region disposed within the circular gates and circular source region disposed around the circular gates. The circular gate and the circular source region may form complete circles.Type: GrantFiled: January 7, 2021Date of Patent: December 31, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Abhishek Banerjee, Peter Moens, Herbert De Vleeschouwer, Peter Coppens
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Patent number: 12183816Abstract: A semiconductor device includes a barrier region and a channel region, source and drain electrodes, and a gate structure that is configured to control a conductive connection between the source and drain electrodes, wherein the barrier region comprises a first barrier layer and a second barrier layer, wherein in a central portion of the device the second barrier layer is the only layer that is disposed over the channel region, wherein in outer lateral portions of the device the first barrier layer is disposed over the channel region, wherein the first and second barrier layers are each III-V semiconductor alloys, and wherein a molar fraction of a second type III element in the central portion is higher than a molar fraction of the second type III element in the first barrier layer.Type: GrantFiled: August 27, 2021Date of Patent: December 31, 2024Assignee: Infineon Technologies Austria AGInventors: Korbinian Reiser, Ingo Daumiller, Lauri Knuuttila, Bhargav Pandya
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Patent number: 12183831Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.Type: GrantFiled: September 29, 2017Date of Patent: December 31, 2024Assignee: Intel CorporationInventors: Van H. Le, Abhishek A. Sharma, Benjamin Chu-Kung, Gilbert Dewey, Ravi Pillarisetty, Miriam R. Reshotko, Shriram Shivaraman, Li Huey Tan, Tristan A. Tronic, Jack T. Kavalieros
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Patent number: 12170328Abstract: A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.Type: GrantFiled: December 15, 2020Date of Patent: December 17, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tatsuya Tominari, Nicholas Stephen Dellas, Qhalid Fareed
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Patent number: 12166103Abstract: A semiconductor device for power amplification includes: a source electrode, a drain electrode, and a gate electrode disposed above a semiconductor stack structure including a first nitride semiconductor layer and a second nitride semiconductor layer; and a source field plate that is disposed above the semiconductor stack structure between the gate electrode and the drain electrode, and has a same potential as a potential of the source electrode. The source field plate has a staircase shape, and even when length LF2 of an upper section is increased for electric field relaxation, an increase in parasitic capacitance Cds generated between the source field plate and a 2DEG surface is inhibited.Type: GrantFiled: May 12, 2021Date of Patent: December 10, 2024Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Katsuhiko Kawashima, Yusuke Kanda, Kenichi Miyajima