Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

Abstract: A transistor includes a first layer comprising a group III-nitride semiconductor. A second layer comprising a group III-nitride semiconductor is disposed over the first layer. A third layer comprising a group III-nitride semiconductor is disposed over the second layer. An interface between the second layer and the third layer form a polarization heterojunction. A fourth layer comprising a group III-nitride semiconductor is disposed over the third layer. An interface between the third layer and the fourth layer forms a pn junction. A first electrical contact pad is disposed on the fourth layer. A second electrical contact pad is disposed on the third layer. A third electrical contact pad is electronically coupled to bias the polarization heterojunction.

Abstract: A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.

Abstract: A group III nitride transistor structure capable of reducing a leakage current and a fabricating method thereof are provided. The group III nitride transistor structure includes: a first heterojunction and a second heterojunction which are laminated, wherein the first heterojunction is electrically isolated from the second heterojunction via a high resistance material and/or insertion layer; a first electrode, a second electrode and a first gate which are matched with the first heterojunction, wherein a third semiconductor is arranged between the first gate and the first heterojunction, and the first gate is also electrically connected with the first electrode; a source, a drain and a second gate which are matched with the second heterojunction, wherein the source and the drain are also respectively electrically connected with the first gate and the second electrode, and a sixth semiconductor is arranged between the second gate and the second heterojunction.

Abstract: An HEMT includes a semiconductor body, which includes a semiconductor heterostructure, and a conductive gate region. The gate region includes: a contact region, which is made of a first metal material and contacts the semiconductor body to form a Schottky junction; a barrier region, which is made of a second metal material and is set on the contact region; and a top region, which extends on the barrier region and is made of a third metal material, which has a resistivity lower than the resistivity of the first metal material. The HEMT moreover comprises a dielectric region, which includes at least one front dielectric subregion, which extends over the contact region, delimiting a front opening that gives out onto the contact region; and wherein the barrier region extends into the front opening and over at least part of the front dielectric subregion.

Abstract: Various light emitting diode device embodiments that include emissive material elements, e.g., core-shell quantum dots, that are either (i) provided in nanoscale holes provided in an insulating layer positioned between an electron supply/transport layer and a hole supply/transport layer, or (ii) provided on a suspension layer positioned above and covering a nanoscale hole in such an insulating layer. Also, various methods of making such light emitting diode devices, including lithographic and non-lithographic methods.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a channel layer disposed on the substrate, and a barrier layer disposed on the channel layer. The semiconductor device further includes a dielectric layer disposed on the barrier layer and defining a first recess exposing a portion of the barrier layer. The semiconductor device further includes a first spacer disposed within the first recess, wherein the first spacer comprises a surface laterally connecting the dielectric layer to the barrier layer.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A gate is disposed on the second III-V compound layer. The gate includes a first P-type III-V compound layer, an undoped III-V compound layer and an N-type III-V compound layer are deposited from bottom to top. The first P-type III-V compound layer, the undoped III-V compound layer, the N-type III-V compound layer and the first III-V compound layer are chemical compounds formed by the same group III element and the same group V element. A drain electrode is disposed at one side of the gate. A drain electrode is disposed at another side of the gate. A gate electrode is disposed directly on the gate.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-V material layer, a first gate, a second gate, and a first passivation layer. The first gate and the second gate are on the III-V material layer. The first passivation layer is on the first gate. A first activation ratio of an element in the first gate is different from a second activation ratio of the element in the second gate.

Abstract: A semiconductor-on-insulator (SOI) substrate with a compliant substrate layer advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N devices (e.g., III-N HFETs) may be formed. The compliant layer may be (111) silicon, for example. The SOI substrate may further include another layer that may have one or more of lower electrical resistivity, greater thickness, or a different crystal orientation relative to the compliant substrate layer. A SOI substrate may include a (100) silicon layer advantageous for integrating Group IV devices (e.g., Si FETs), for example. To reduce parasitic coupling between an HFET and a substrate layer of relatively low electrical resistivity, one or more layers of the substrate may be removed within a region below the HFETs. Once removed, the resulting void may be backfilled with another material, or the void may be sealed, for example during back-end-of-line processing.

Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, and first, second, and third semiconductor regions. The third electrode is between the first electrode and the second electrodes. The first semiconductor region includes Alx1Ga1-x1N and includes first to seventh partial regions. The fourth partial region is between the first partial region and the third partial region. The fifth partial region is between the third partial region and the second partial region. The second semiconductor region includes Alx2Ga1-x2N and includes first and second semiconductor portions. The sixth partial region is between the fourth partial region and the first semiconductor portion. The seventh partial region is between the fifth partial region and the second semiconductor portion. The third semiconductor region includes Alx3Ga1-x3N and includes a first semiconductor film part. The first semiconductor film part is between the sixth partial region and the third electrode.

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

Abstract: A High Electron Mobility Transistor (HEMT) device can include an AlN buffer layer on a substrate and an epi-GaN channel layer on the AlN buffer layer. An AlN barrier layer can be on the Epi-GaN channel layer to provide a channel region in the epi-GaN channel layer. A GaN drain region can be recessed into the epi-GaN channel layer at a first end of the channel region and a GaN source region can be recessed into the epi-GaN channel layer at a second end of the channel region opposite the first end of the channel region. A gate electrode can include a neck portion with a first width that extends a first distance above the AlN barrier layer between the GaN drain region and the GaN source region to a head portion of the gate electrode having a second width that is greater than the first width.

Abstract: Structures, devices and methods are provided for forming an interface protection layer (204) adjacent to a fully or partially recessed gate structure (202) of a group III nitride, a metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) device or a metal-insulator-semiconductor field-effect transistor (MIS-FET) device, and forming agate dielectric (114) disposed the interface protection layer (204).

Abstract: An N-polar III-N high-electron mobility transistor device can include a III-N channel layer over an N-face of a III-N backbarrier, wherein a compositional difference between the channel layer and the backbarrier causes a 2DEG channel to be induced in the III-N channel layer adjacent to the interface between the III-N channel layer and the backbarrier. The device can further include a p-type III-N layer over the III-N channel layer and a thick III-N cap layer over the p-type III-N layer. The III-N cap layer can cause an increase in the charge density of the 2DEG channel directly below the cap layer, and the p-type III-N layer can serve to prevent a parasitic 2DEG from forming in the III-N cap layer.

Abstract: A semiconductor device 1 has an electrode structure that includes source electrodes 3, a gate electrode 4, and drain electrodes 5 disposed on a semiconductor laminated structure 2 and extending in parallel to each other and in a predetermined first direction and a wiring structure that includes source wirings 9, drain wirings 10, and gate wirings 11 disposed on the electrode structure and extending in parallel to each other and in a second direction orthogonal to the first direction. The source wirings 9, the drain wirings 10, and the gate wirings 11 are electrically connected to the source electrodes 3, the drain electrodes 5, and the gate electrode 4, respectively. The semiconductor device 1 includes a conductive film 8 disposed between the gate electrode 4 and the drain wirings 10 and being electrically connected to the source electrodes 3.

Abstract: There is provided a semiconductor layer structure (100) comprising: a Si substrate (102) having a top surface (104); a first semiconductor layer (110) arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures (112) arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; a second semiconductor layer (120) arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising AlxGa1-xN, wherein 0?x?0.95; a third semiconductor layer (130) arranged on said second semiconductor layer, the third semiconductor layer comprising AlyGa1-yN, wherein 0?y?0.95; and a fourth semiconductor layer (140) arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN. There is also provided a high-electron-mobility transistor device and methods of producing such structures and devices.

Abstract: An inventive solid-state imaging apparatus is provided which can improve the efficiency of the electric carrier transfer from a photoelectric conversion portion to an electric-carrier accumulation portion. The solid-state imaging apparatus includes an active region having the photoelectric conversion portion, the electric-carrier accumulation portion, and a floating diffusion, and an element isolation region having an insulator defining the active region. In planer view, the width of the active region in the electric-carrier accumulation portion under a gate of the first transfer transistor is larger than the width of the active region in the photoelectric conversion portion under the gate of the first transfer transistor.

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate.