Abstract: Various embodiments of the present application are directed to a narrow band filter with high transmission and an image sensor comprising the narrow band filter. In some embodiments, the filter comprises a first distributed Bragg reflector (DBR), a second DBR, a defect layer between the first and second DBRs, and a plurality of columnar structures. The columnar structures extend through the defect layer and have a refractive index different than a refractive index of the defect layer. The first and second DBRs define a low transmission band, and the defect layer defines a high transmission band dividing the low transmission band. The columnar structures shift the high transmission band towards lower or higher wavelengths depending upon a refractive index of the columnar structures and a fill factor of the columnar structures.

Abstract: Various embodiments of the present application are directed to a narrow band filter with high transmission and an image sensor comprising the narrow band filter. In some embodiments, the filter comprises a first distributed Bragg reflector (DBR), a second DBR, a defect layer between the first and second DBRs, and a plurality of columnar structures. The columnar structures extend through the defect layer and have a refractive index different than a refractive index of the defect layer. The first and second DBRs define a low transmission band, and the defect layer defines a high transmission band dividing the low transmission band. The columnar structures shift the high transmission band towards lower or higher wavelengths depending upon a refractive index of the columnar structures and a fill factor of the columnar structures.

Abstract: A sensor includes a sensor array. The sensor array includes a plurality of passive imaging pixels and a plurality of time of flight (TOF) imaging pixels. A method of imaging includes collecting passive imaging data from a sensor array and collecting time of flight (TOF) imaging data from the sensor array. Collecting passive imaging data and collecting TOF imaging data can be performed at least partially at the same time and along a single optical axis without parallax.

Abstract: Disclosed is a quantum dot light-emitting diode including a positive electrode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and a negative electrode, wherein the hole injection layer is a p-type oxide semiconductor represented by Formula 1 below: Cu2Sn2-XS3—(GaX)2O3,??[Formula 1] wherein X is greater than 0.2 and less than 1.5 (0.2<x<1.5).

Abstract: Provided are a semiconductor photodiode which achieves a higher response rate in a state in which light receiving sensitivity is maintained. The semiconductor photodiode includes a p-type semiconductor contact layer, an n-type semiconductor contact layer, and a light absorption layer. The light absorption layer includes a first semiconductor absorption layer having a thickness Wd and a p-type second semiconductor absorption layer having a thickness Wp. The first semiconductor absorption layer and the second absorption layer are made of the same composition. The first semiconductor absorption layer is depleted, and the second semiconductor absorption layer maintains an electric charge neutral condition except for a region near an interface with the first semiconductor absorption layer. A relationship between the thickness Wd and the thickness Wp satisfies 0.47?Wp/(Wp+Wd)?0.9.

Abstract: Some embodiments of this disclosure provide a semiconductor device. The semiconductor device includes: a substrate; a barrier layer, disposed on the substrate; a first channel layer, disposed on the barrier layer; a first gate conductor, disposed on the first channel layer; and a first doped semiconductor layer, disposed between the first gate conductor and the first channel layer, where a forbidden band width of the barrier layer is greater than a forbidden band width of the first channel layer.

Abstract: An organic light emitting diode display is discussed. The organic light emitting diode display can include a substrate including a thin film transistor region in which a thin film transistor and an organic light emitting diode connected to the thin film transistor are disposed, and an auxiliary electrode region in which an auxiliary electrode is disposed, a barrier disposed on the auxiliary electrode, a cathode included in the organic light emitting diode, divided by the barrier, and exposing at least a portion of the auxiliary electrode, an end of the cathode being in direct contact with the auxiliary electrode, and a cover layer disposed on the cathode, the cover layer having continuity to cover the barrier and the auxiliary electrode.

Abstract: According to an embodiment, a semiconductor memory device includes: a first stacked body including a first semiconductor layer, a first memory film, a second semiconductor layer and a first insulating layer; a joining member provided on the first semiconductor layer, the second semiconductor layer, and the first insulating layer; a first layer provided above the joining member and covering the first semiconductor layer and the first memory film; a second layer provided above the joining member, located away from the first layer as viewed in a second direction perpendicular to the first direction, and covering the second semiconductor layer and the second memory film; a second stacked body including a third semiconductor layer, a fourth semiconductor layer, a fourth memory film and a second insulating layer.

Abstract: Methods of forming a gate cut isolation for an SRAM include forming a first and second active nanostructures adjacent to each other and separated by a space; forming a sacrificial liner over at least a side of the first active nanostructure facing the space, causing a first distance between a remaining portion of the space and the first active nanostructure to be greater than a second distance between the remaining portion of the space and the second active nanostructure. A gate cut isolation is formed in the remaining portion of the space such that it is closer to the second active nanostructure than the first active nanostructure. The sacrificial liner is removed, and gates formed over the active nanostructures with the gates separated from each other by the gate cut isolation. An SRAM including the gate cut isolation and an IC structure including the SRAM are also included.

Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.

Abstract: A display device includes a substrate including a display area and a non-display area outside the display area, a plurality of pixels located in the display area, a driving circuit driving the pixels, and a pad portion located in the non-display area and electrically connected to the driving circuit through a plurality of outer wirings. The pad portion includes a plurality of pad wirings each electrically connected to corresponding ones of the outer wirings. The pad wirings includes a first pad wiring and a second pad wiring separated from each other. The first pad wiring includes a first electrode layer, an insulating layer on the first electrode, and a second electrode layer on the insulating layer in a stacking direction, the second electrode layer being connected to the first electrode layer. The second pad wiring includes the first electrode layer but not the second electrode layer.

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.

Abstract: The light emitting element includes: first and second light emitting cells each including an n-side semiconductor layer, an active layer and a p-side semiconductor layer; a first insulating film covering the first and second light emitting cells, and provided with first p-side and first n-side openings; a wiring electrode connected to the first light emitting cell at the first n-side opening, and connected to the second light emitting cell at the first p-side opening; a first electrode connected to the first light emitting cell; a second electrode connected to the second light emitting cell; a second insulating film provided with a second p-side opening formed above the first electrode, a second n-side opening formed above the second electrode, and a third opening formed above the wiring electrode; a first external connection portion connected to the first electrode; and a second external connection portion connected to the second electrode.

Abstract: A method is presented for obtaining a controllable resistance change in a battery-like device. The method includes depositing a first lithium-compound based layer in direct contact with a bottom electrode, depositing an electrolyte layer in direct contact with the first lithium-compound based layer, depositing a second lithium-compound based layer in direct contact with the electrolyte layer, forming a top electrode in direct contact with the second lithium-compound based layer, and applying electrical pulses between the top and bottom electrodes to trigger lithium ion transport to modify lithium concentrations in the first and second lithium-compound based layers.

Abstract: According to a flexible OLED device production method of the present disclosure, a multilayer stack (100) is provided, the multilayer stack including a base (10), a functional layer region (20) which includes a TFT layer and an OLED layer, a flexible film (30) provided between the base and the functional layer region and supporting the functional layer region, and a dielectric multilayer film mirror (36) provided between the flexible film and the functional layer region. The flexible film is irradiated with lift-off light (216) transmitted through the base, whereby the flexible film is delaminated from the base.

Abstract: In an oxide semiconductor device including an active layer region constituted by an oxide semiconductor, stability when a stress is applied is improved. The oxide semiconductor device includes an active layer region constituted by an oxide semiconductor of indium (In), gallium (Ga), and zinc (Zn), wherein the active layer region contains an element selected from titanium (Ti), zirconium (Zr), and hafnium (Hf) that are Group 4 elements, or carbon (C), silicon (Si), germanium (Ge), and tin (Sn) that are Group 14 elements at a number density in a range of 1×1016 to 1×1020 cm?3.

Abstract: Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

Abstract: A semiconductor device includes a fin structure, a first conductive line, a second conductive line and a first conductive rail. The fin structure is disposed on a substrate. The first conductive line is arranged to wrap a first portion of the fin structure. The second conductive line is attached on a second portion of the fin structure. The second portion is different from the first portion. The first conductive rail is disposed in a same layer as the first conductive line and the second conductive line on the substrate. The first conductive rail is attached on one end of the first conductive line and one end of the second conductive line for electrically connecting the first conductive line and the second conductive line.