Patents Examined by Grant Withers
  • Patent number: 10229944
    Abstract: An inventive solid-state imaging apparatus is provided which can improve the efficiency of the electric carrier transfer from a photoelectric conversion portion to an electric-carrier accumulation portion. The solid-state imaging apparatus includes an active region having the photoelectric conversion portion, the electric-carrier accumulation portion, and a floating diffusion, and an element isolation region having an insulator defining the active region. In planer view, the width of the active region in the electric-carrier accumulation portion under a gate of the first transfer transistor is larger than the width of the active region in the photoelectric conversion portion under the gate of the first transfer transistor.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: March 12, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yusuke Onuki, Masahiro Kobayashi, Takafumi Miki
  • Patent number: 10229998
    Abstract: Variations in height of a top of an element isolation region, which is embedded in a trench surrounding the periphery of a fin having a channel region of a split-gate MONOS memory, are suppressed to improve reliability of a semiconductor device. An element isolation region embedded in a trench between a plurality of fins, which are part of a semiconductor substrate in a memory cell region and protrude above the semiconductor substrate, is comprised of an insulating film covering the bottom of the trench and a silicon nitride film covering the top of the insulating film.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 12, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuyoshi Mihara
  • Patent number: 10224436
    Abstract: A semiconductor device includes a semiconductor substrate, a silicon carbide semiconductor layer disposed on the semiconductor substrate, and a termination region disposed in the silicon carbide semiconductor layer. The termination region has a guard ring region and an FLR region which is disposed to surround the guard ring region while being separated from the guard ring region, the FLR region including a plurality of rings. The termination region includes a sector section, and in the sector section, an inner circumference and an outer circumference of at least one of the plurality of rings and an inner circumference and an outer circumference of the guard ring region have a same first center of curvature, the first center of curvature being positioned inside the inner circumference of the guard ring region, and a radius of curvature of the inner circumference of the guard ring region is 50 ?m or less.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: March 5, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Masao Uchida
  • Patent number: 10217898
    Abstract: A semiconductor device comprises a layer sequence formed by a plurality of polar single crystalline semiconductor material layers that each have a crystal axis pointing in a direction of crystalline polarity and a stacking direction of the layer sequence. A core layer sequence is formed by an active region made of an active layer stack or a plurality of repetitions of the active layer stack. The active layer stack has an active layer having a first material composition associated with a first band gap energy, and carrier-confinement layers embedding the active layer on at least two opposite sides thereof, having a second material composition associated with a second band gap energy larger than the first band gap energy. A pair of polarization guard layers is arranged adjacent to the active region and embedding the active region on opposite sides thereof. Both polarization guard layers have the first material composition.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 26, 2019
    Assignee: TECHNISCHE UNIVERSITÄT BERLIN
    Inventors: Gerald Pahn, Gordon Callsen, Axel Hoffmann
  • Patent number: 10209595
    Abstract: Provided are an array substrate and a manufacturing method therefor, and a display panel. The array substrate comprises: a base substrate; a data line and a passivation layer which are formed on the base substrate; a common electrode layer formed on the passivation layer; and a shielding electrode layer and a barrier layer which are formed on the base substrate, wherein the shielding electrode layer is arranged between the data line and the passivation layer, the barrier layer is arranged between the data line and the shielding electrode layer, the shielding electrode layer is grounded, and the barrier layer is made of a material with an insulation function.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: February 19, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xiao Wang
  • Patent number: 10199311
    Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: February 5, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, Soon Wei Wang, Chee Hiong Chew
  • Patent number: 10199506
    Abstract: The embodiments of the present invention disclose a low temperature poly-silicon (LTPS) transistor array substrate and a method of fabricating the same, and a display device. The LTPS transistor array substrate comprises a substrate; a poly-silicon semiconductor active region provided on the substrate; a gate insulated from the poly-silicon semiconductor active region; and a dielectric spacer region provided on a side wall of the gate, wherein a portion of the poly-silicon semiconductor active region corresponding to the dielectric spacer region comprises a buffer region, and the dielectric spacer region surrounds the side wall of the gate and covers the buffer region.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: February 5, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaoyong Lu, Zheng Liu, Xiaolong Li, Dong Li, Huijuan Zhang, Liang Sun
  • Patent number: 10193024
    Abstract: An optoelectronic semiconductor chip includes an active region arranged between a first semiconductor layer and a second semiconductor layer and generates or receives electromagnetic radiation, the first semiconductor layer electrically conductively connects to a first contact, the first contact is formed on a front side of the chip next to the active region, the second semiconductor layer electrically conductively connects to a second contact, the second contact is arranged on the front side of the chip next to the active region, and an electrically insulating separating layer that electrically insulates a rear side of the chip from the active region of the semiconductor chip, and an electrically insulating separating layer includes at least one first separating layer having at least one atomic layer or at least one molecular layer and is deposited by atomic layer deposition or molecular layer deposition.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: January 29, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Rainer Hartmann, Martin Mandl, Simeon Katz, Andreas Rückerl
  • Patent number: 10192887
    Abstract: The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yun Y. Wang, Oh-Jung Kwon, Stephen G. Fugardi, Sean M. Dillon
  • Patent number: 10192929
    Abstract: A three-dimensional memory device includes conductive structures located over a substrate, an alternating stack of insulating layers and electrically conductive layers formed over the conductive structures, and an array of memory structures formed through the alternating stack. Each of the memory structures includes memory elements located at levels of the electrically conductive layers. A contact region can be formed on the alternating stack. Two-stage contact via cavities having a greater width above a top surface of a respective electrically conductive layer and having a narrower width through the alternating stack can be formed in the contact region. Upper insulating spacers and lower insulating spacers are formed such that annular surfaces of the respective electrically conductive layer are physically exposed. Two-stage contact via structures can provide electrical contact between the electrically conductive layers and the conductive structures.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: January 29, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Yoshio Mori
  • Patent number: 10186524
    Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 22, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David Pritchard, Lixia Lei, Deniz E. Civay, Scott D. Luning, Neha Nayyar
  • Patent number: 10170615
    Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type. The source region and the drain region are arranged in a first direction parallel to a first main surface of a semiconductor substrate. The semiconductor device further includes a layer stack having a drift layer of the first conductivity type and a compensation layer of a second conductivity type. The drain region is electrically connected with the drift layer. The semiconductor device also includes a connection region of the second conductivity type extending into the semiconductor substrate, the connection region being electrically connected with the compensation layer, wherein the buried semiconductor portion does not fully overlap with the drift layer.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: January 1, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Anton Mauder, Andreas Meiser, Till Schloesser
  • Patent number: 10170505
    Abstract: A display apparatus capable of reducing a defect rate during manufacturing and utilizing thereof, the display apparatus includes a substrate comprising a display area and a peripheral area outside the display area; a display unit over an upper surface of the substrate to correspond to the display area; and a protective film including a protective film base and an adhesive layer, the protective film being attached to the lower surface of the substrate by the adhesive layer, wherein the protective film base includes a first protective film base corresponding at least to the display area, and a second protective film base having physical properties that are different from physical properties of the first protective film base and corresponding to at least a part of the peripheral area.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: January 1, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sangwol Lee, Sungku Kang, Jinkyu Kim
  • Patent number: 10170481
    Abstract: A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a plurality of bit lines, a gate, a spacer layer and a first spacer. The substrate has a memory cell region and a periphery region, the a plurality of bit lines are disposed on the substrate, within the memory cell region, and the gate is disposed on the substrate, within the periphery. The spacer layer covers the bit lines and a sidewall of the gate. The first spacer is disposed at two sides of the gate, covers on the spacer layer.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: January 1, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho, Tsung-Ying Tsai
  • Patent number: 10163972
    Abstract: A method of forming a semiconductor image sensing device includes: providing a semiconductor substrate; forming a radiation sensitive region and a peripheral region in the semiconductor substrate, wherein the peripheral region surrounds the radiation sensitive region and includes a top surface projected from a backside of the semiconductor substrate and a sidewall coplanar with a sidewall of the semiconductor substrate and perpendicular to the top surface; forming a photon blocking spacer in the peripheral region, wherein the photon blocking spacer covers a portion of the sidewall of the peripheral region; and forming an anti reflective coating adjacent to the photon blocking layer.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Wen Hsu, Jung-I Lin, Ching-Chung Su, Jiech-Fun Lu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 10158036
    Abstract: There is to provide a semiconductor device including a light receiving element capable of reducing the manufacturing cost and improving the optical performance of the light receiving element. For example, a p type germanium layer, an intrinsic germanium layer, and an n type germanium layer forming the structure body of a Ge photodiode are formed according to a continuous selective epitaxial growth. An insulating film having an opening portion is formed on the silicon layer of a SOI substrate, and an intrinsic germanium layer is formed bulging from the opening portion to above the insulating film. In short, by using the insulating film having the opening portion, the cross section of the intrinsic germanium layer is formed into a mushroom shape.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 18, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuya Usami
  • Patent number: 10153194
    Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Marcello D. Mariani, Anna Maria Conti, Sara Vigano
  • Patent number: 10147785
    Abstract: In at least some embodiments, a semiconductor device structure comprises a first surface comprising a source and a gate; a second surface comprising a drain; a substrate of a first type, wherein the substrate is in contact with the drain; a first column in contact with the substrate and the first surface of the device, the first column comprising a dielectric material; and a mirroring axis, wherein a centerline of the first column is disposed along the mirroring axis, forming a first device side and a second device side, wherein the first device side mirrors the second device side.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: December 4, 2018
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jaume Roig-Guitart, Filip Bauwens
  • Patent number: 10147852
    Abstract: A light-emitting device includes a light-emitting element, a cover layer, and an anti-adhesion layer. The light-emitting element has a top surface, a bottom surface and a side surface. The cover layer covers the light-emitting element and includes a first transparent binder. The anti-adhesion layer includes a flouro-resin or a fluoride compound and disposed on the cover layer and the top surface as an outermost layer of the light-emitting device. The anti-adhesion layer has a hardness greater than a hardness of the cover layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 4, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Ching-Tai Cheng, Yih-Hua Renn, Chun-Hua Shih
  • Patent number: 10141316
    Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Seok Lee, Jeong Seop Shim, Mi Na Lee, Augustin Jinwoo Hong, Je Min Park, Hye Jin Seong, Seung Min Oh, Do Yeong Lee, Ji Seung Lee, Jin Seong Lee