Abstract: A back-side imager includes a matrix of photosites in an active layer. An interconnect layer covers the active layer. A layer of germanium is positioned between the active layer and the interconnect layer.

Abstract: An image sensor includes a semiconductor material including a plurality of photodiodes disposed in the semiconductor material. The image sensor also includes a first insulating material disposed proximate to a frontside of the semiconductor material, and an interconnect disposed in the first insulating material proximate to the frontside of the semiconductor material. A metal pad extends from a backside of the semiconductor material through the first insulating material and contacts the interconnect. A metal grid is disposed proximate to the backside of the semiconductor material, and the semiconductor material is disposed between the metal grid and the first insulating material disposed proximate to the frontside.

Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.

Abstract: NW-FET sensor comprising: first and second semiconducting nanowires; a first semiconducting source portion, of which the first and second parts doped differently from each other are connected to the first ends of the nanowires; a second semiconducting drain portion, of which the first and second parts doped differently from each other are connected to the second ends of the nanowires; a first electrical contact placed on the first semiconducting portion and electrically connected to the first and second parts of the first semiconducting portion; a second electrical contact placed on the second semiconducting portion and electrically connected to the first and second parts of the second semiconducting portion;

Abstract: A semiconductor device includes a middle field stop layer having a first conductivity type impurity concentration higher than a drift layer and arranged at a position in the drift layer. A ratio of a depth of the position of the middle field stop layer from a front surface of a semiconductor substrate to a thickness of the semiconductor substrate is equal to or greater than fifteen percent and equal to or less than thirty-five percent. When an IGBT is arranged in the semiconductor device, vibration of a collector voltage waveform in a switching off of the IGBT is restricted. When a diode is arranged in the semiconductor device, vibration of a recovery waveform in a recovery operation of the diode is restricted. Accordingly, at least one of the vibrations of the recovery waveform and the collector voltage waveform in the switching is restricted.

Abstract: The present disclosure provides a method for fabricating a compound varactor. The method includes steps of depositing a collector layer, depositing a first base layer arranged in a first plurality of parallel fingers directly onto the collector layer, and depositing a second base layer arranged in a second plurality of parallel fingers that are interleaved with the first plurality of parallel fingers directly onto the collector layer.

Abstract: A light-emitting device includes a light-emitting element, a cover layer, and an anti-adhesion layer. The light-emitting element has a top surface, a bottom surface and a first side surface. The cover layer covers the light-emitting element and includes a first transparent binder and a plurality of wavelength conversion particles dispersed within the first transparent binder. The anti-adhesion layer includes a fluoro-containing material, and is disposed on the cover layer and the top surface.

Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a base substrate, the base substrate includes a base terminal; an integrated circuit device on the base substrate; a bottom conductive joint on the base terminal; a conductive ball on the bottom conductive joint, the conductive ball includes a core body; and an interposer over the conductive ball.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type.

Abstract: An optoelectronic device, comprising: a first semiconductor layer comprising four boundaries, a corner formed by two of the neighboring boundaries, a first surface, and a second surface opposite to the first surface; a second semiconductor layer formed on the first surface of the first semiconductor layer; a second conductive type electrode formed on the second semiconductor layer; and two first conductive type electrodes formed on the first surface, wherein the first conductive type electrodes are separated and formed a pattern.

Abstract: The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.

Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

Abstract: A method of forming electrical contacts on a diamond substrate comprises producing a plasma ball using a microwave plasma source in the presence of a mixture of gases. The mixture of gases include a source of a p-type or an n-type dopant. The plasma ball is disposed at a first distance from the diamond substrate. The diamond substrate is maintained at a first temperature. The plasma ball is maintained at the first distance from the diamond substrate for a first time, and a UNCD film, which is doped with at least one of a p-type dopant and an n-type dopant, is disposed on the diamond substrate. The doped UNCD film is patterned to define UNCD electrical contacts on the diamond substrate.

Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

Abstract: A complementary logic device includes i) a substrate, ii) a first semiconductor device located on the substrate and including a first channel layer, a carrier supply layer for supplying a carrier to the channel layer, and an upper cladding layer and a lower cladding layer respectively located at upper and lower portions of the channel layer, iii) a second semiconductor device located on the substrate and including a structure the same or similar to that of the first semiconductor device, iv) a source electrode located on the two semiconductors and made of a ferromagnetic body, v) a drain electrode located on the two semiconductors and made of a ferromagnetic body, and vi) a gate electrode located on the two semiconductors and located between the two electrodes so that a gate voltage is applied thereto to control a spin of electrons passing through the two channel layers.

Abstract: The present disclosure provides an array substrate and a method of manufacturing the same, and a display device comprising the array substrate. The array substrate comprises: a substrate; gate lines and data lines arranged to intersect one another on the substrate; a gate line connection conducting wire layer provided between the gate lines and the substrate and below the gate lines; and/or, a data line connection conducting wire layer provided in regions of the array substrate corresponding to the data lines; wherein the gate line connection conducting wire layer is electrically isolated from the data line connection conducting wire layer.

Abstract: A method for fabricating high-resolution features in a deep recess includes etching a cavity in a substrate, fabricating at least one focusing pattern on a bottom of the cavity, wherein fabricating the focusing pattern comprises coating a first photoresist on the bottom of the cavity, patterning the first photoresist to define a focusing etch area using contact lithography, and etching the focusing etch area, coating a second photoresist on the bottom of the cavity, using the focusing pattern to focus a high resolution lithography tool at the bottom of the cavity to pattern the second photoresist to define a microfabrication feature area; and forming a microfabrication feature in the microfabrication feature area.

Abstract: A semiconductor device is provided. A fin is disposed on a substrate. The fin, including a first material and a second material, includes a first fin area and a second fin area. A gate structure is disposed on the first fin area. A source region is in contact with the second fin area. The first fin area includes the first material at a first concentration, the second fin area includes the first material at a second concentration which is greater than the first concentration.

Abstract: A silicon-doped n-type aluminum nitride monocrystalline substrate wherein, at a photoluminescence measurement at 23° C., a ratio (I1/I2) between the emission spectrum intensity (I1) having a peak within 370 to 390 nm and the emission peak intensity (I2) of the band edge of aluminum nitride is 0.5 or less; a thickness is from 25 to 500 ?m; and a ratio (electron concentration/silicon concentration) between the electron concentration and the silicon concentration at 23° C. is from 0.0005 to 0.001.

Abstract: Methods of producing integrated circuits with interposers and integrated circuits produced from such methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes producing an interposer with an insulation plate and a plurality of through vias passing through the insulation plate. The interposer has a prime area and an in prime area. A prime area test circuit is formed in the prime area, where the prime area test circuit includes a portion of the plurality of through vias that are electrically connected in series.