Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.

Abstract: A method of predicting the electromagnetic noise emitted by a digital circuit on an integrated circuit is disclosed. In accordance with the illustrative embodiment, the output of each digital circuit element in the digital circuit is considered as a bit stream. All of these bits streams are, in aggregate, considered as a noise source that is characterized by a power spectral density, S(?). The effect of the noise source on an analog circuit can be modeled as a lumped circuit, wherein the lumped circuit contains a noise source that represents the digital circuit; a multi-port network, also referred to as a lumped element, that represents that portion of the substrate between the digital circuit and the analog circuit; and a multi-port network that represents the analog circuit.

Abstract: A system and method for processing a workpiece, includes workpiece processors. A robot is moveable within an enclosure to load and unload workpieces into and out of the processors. A processor includes an upper rotor having a central air flow opening. The upper rotor is magnetically driven into engagement with a lower rotor to form a workpiece processing chamber. A moveable drain mechanism aligns different drain paths with the processing chamber so that different processing fluids may be removed from the processing chamber via different drain paths. A moveable nozzle positioned in the air flow opening distributes processing fluid to the workpiece. The processing fluid is distributed across the workpiece surface, via centrifugal force generated by spinning the processing chamber, and removed from the processing chamber via the moveable drain mechanism.

Abstract: A method for fabricating a semiconductor component includes: deposition of a polysilicon layer on a substrate, deposition of a precursor layer on the polysilicon layer, and deposition of a protective layer on the precursor layer. A crystalline transformation occurs in the precursor layer at a first temperature to form an electrode layer. The layers are patterned to form an electrode stack, and the polysilicon layer is oxidized at a second temperature such that no crystalline transformation occurs in the electrode layer.

Abstract: A thermal nitride film is formed as a gate insulating film on a silicon substrate, and after a gate electrode material is formed on the insulating film, it is patterned to form gate electrodes. After processing the electrodes, part of the gate insulating film other than a portion thereof which lies under the gate electrodes is removed. Further, an insulating film (a post oxidation film) is formed on side walls and upper surfaces of the stacked gate structures and the exposed main surface of the silicon substrate by use of thermal oxidation method.

Abstract: To provide a design verification device, a method and a memory medium therefor, for a semiconductor integrated circuit, capable of effectively introducing the formal verification in a higher-level design and capable of constructing a high-speed function verification environment with high verification assurance.

Abstract: A semiconductor device efficiently providing the DC currents required in both discrete and integrated circuits operated at low DC supply voltages. The device disclosed in the present invention is an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET). The device consists of an epitaxial layer on the surface of a substrate, both of which are doped with the same polarity. The epitaxial layer has a graded doping profile with doping density increasing with distance from the substrate. A grill-like structure is constructed within the upper and lower bounds of, and extending throughout the length and width of the epitaxial layer, and is doped with a polarity opposite to that of the epitaxial layer. A first electrical connection made to the exposed side of the substrate is defined as the drain electrode. A second electrical connection made to the exposed surface of the epitaxial layer is defined as the source electrode.

Abstract: Method for determining the robustness of a device to soft errors generated by alpha-particle and/or cosmic ray strikes.

Abstract: A method of manufacturing a field emission device. The method having the steps of preparing a field emitter array having a plurality of electron emitting elements made of conductive material capable of emitting electrons upon application of an electric field, and impinging particle beams upon the plurality of electron emitting elements at the same time to mill a tip of each electron emitting element and form a sharp tip.

Abstract: An active element has first and second regions and a control electrode. Carriers move between the first and second regions in a first direction. A motion of carriers is controlled by an electric signal applied to the control electrode. The first and second regions and control electrode extend in a second direction crossing the first direction from an input terminal to an output terminal. A conductive region is electrically connected to the first region from the input terminal to the output terminal. A trigger line extending in the second direction propagates an electric signal from the input terminal to the output terminal. The electric signal propagating the trigger line is applied to the control electrode at a corresponding position in the second direction. An output line extending in the second direction propagates an electric signal from the input terminal to the output terminal.

Abstract: There is disclosed a method and apparatus for forming a thin film of a composite metal compound. Independent targets formed of at least two different metals are sputtered so as to form on a substrate an ultra-thin film of a composite metal or an incompletely-reacted composite metal. The ultra-thin film is irradiated with the electrically neutral, activated species of a reactive gas so as to convert the composite metal or the incompletely-reacted composite metal to a composite metal compound through the reaction of the ultra-thin film with the activated species of the reactive gas. The formation of the ultra-thin film and the conversion to the composite metal compound are sequentially repeated so as to form on the substrate a thin film of the composite metal compound having a desired thickness.

Abstract: A method is provided for forming a copper interconnect, the method including forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first copper structure in the first opening. The method also includes forming a sacrificial dielectric layer above the first dielectric layer and above the first copper structure, forming a second opening in the sacrificial dielectric layer above at least a portion of the first copper structure, and forming a second copper structure in the second opening, the second copper structure contacting the at least the portion of the first copper structure. The method further includes removing the sacrificial dielectric layer above the first dielectric layer and adjacent the second copper structure, and forming the copper interconnect by annealing the second copper structure and the first copper structure.

Abstract: Semiconductor device and method for manufacturing the same prevent the spread of a tungsten film out of an opening portion of a contact hole when the tungsten is grown in the contact hole and avoid inferior wiring shape and inter-wiring shirt-circuit. After a titanium/titanium nitride film is formed along an inner surface of the contact hole, a photo-resist film is applied. Then, the photo-resist film is etched away until a distance from an upper end of the contact hole to the surface of photo-resist film is not smaller than one-half of a width of the contact hole when the titanium/titanium nitride film is formed. After the titanium/titanium nitride film is etched by using the photo-resist as a mask, the photo-resist film is removed and a tungsten layer is selectively grown by using the titanium/titanium nitride film as a seed.

Abstract: Methods of optimizing a preheat recipe for rapid thermal processing workpieces are provided. In one aspect, a method of manufacturing is provided that includes preheating a rapid thermal processing chamber according to a preheating recipe and processing a first plurality of workpieces in the rapid thermal processing chamber. Parameter measurements are performed on a first workpiece and a second workpiece of the first plurality of workpieces. The parameter measurements are indicative of processing differences between the first and second workpieces. An output signal is formed corresponding to the parameter measurements and a control signal based on the output signal is used to adjust the preheating recipe for preheating the rapid thermal processing chamber for processing a second plurality of workpieces in the rapid thermal processing chamber to reduce processing differences between first and second workpieces of the second plurality of workpieces.

Abstract: A low dielectric constant material and a process for controllably reducing the dielectric constant of a layer of such material is provided and comprises the step of exposing the layer of dielectric material to a concentration of an oxygen plasma at a temperature and a pressure sufficient for the oxygen plasma to etch the layer of dielectric material to form voids in the layer of dielectric material. The process may also include the step of controlling the reduction of the dielectric constant by controlling the size and density of the voids. The size and density of the voids can be controlled by varying the pressure under which the reaction takes place, by varying the temperature at which the reaction takes place, by varying the concentration of the oxygen plasma used in the reaction or by varying a combination of these parameters. The process of the present invention is particularly useful in the fabrication of semiconductor devices.

Abstract: A new method is provided for the creation of a high Q inductor. STI trenches are etched for both the active region and the inductor region. The location of the STI region for the inductor is removed from the active region by a significant distance. A thick layer of photoresist is deposited over the surface of the substrate that does not coincide with the surface of the substrate over which the inductor is to be created. A high-energy ion implant is performed after which the thick layer of photoresist is removed. The inside surfaces of the STI trenches are lined after which the STI trenches are filled and the process of creating the semiconductor device proceeds, using conventional methods of fabrication of active components and the inductor whereby the inductor is created overlying the surface of the substrate into which the high-energy ion implant has been performed.

Abstract: The invention provides a number of semiconductor substrate manufacturing methods with which, in manufacturing a semiconductor substrate having a semiconductor layer in an insulated state on a supporting substrate, it is possible to obtain a thick semiconductor layer with a simple process and cheaply while reducing impurity contamination of the semiconductor layer to a minimum.

Abstract: A method for using CMP processes in the salicide process for preventing bridging.

Abstract: A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes providing a semiconductor substrate and thermally growing a first silicon oxide layer overlying the semiconductor substrate. A thermal anneal is performed after growing the first silicon oxide layer in an ambient atmosphere of at least one of nitric oxide, nitrous oxide and ammonia. In this regard, nitrogen is incorporated into the first silicon oxide layer which leads to a better performance and a higher quality of the ONO structure. A silicon nitride layer is formed to overlie the first silicon oxide layer; and a second layer of silicon oxide is formed to overlie the silicon nitride layer to complete the ONO structure.

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.