Abstract: In a method for manufacturing a semiconductor device, an impurity diffusion region is formed within a semiconductor substrate. Then, a chemical dry etching process or a heating process is carried out to remove a contamination layer from the impurity diffusion region. Then, a silicon layer is selectively grown on the impurity diffusion region.

Abstract: There is provided the method of manufacturing a polycrystalline semiconductor thin film, in which an amorphous semiconductor thin film is formed on an insulating substrate, and the amorphous semiconductor thin film is transformed into a polycrystalline semiconductor thin film. In this method, an energy beam is irradiated onto a predetermined region of the amorphous semiconductor thin film via a mask prepared by forming energy beam transmitting regions on a transparent plate as a plurality of patterns, and the region on which the energy beam is irradiated is changed so as to move the predetermined region on the amorphous semiconductor thin film in order.

Abstract: A semiconductor device includes: a field oxide layer formed on a semiconductor substrate; a transistor having an active region formed on a semiconductor substrate; an interlayer insulating layer formed on the transistor and the field oxide; and a tapered contact hole exposing the active region adjacent to the field oxide layer, wherein an upper portion of the tapered contact hole is wider than a lower portion thereof so that the field oxide is not etched during the contact hole etching process.

Abstract: A composite dielectric layer and method of forming the composite dielectric layer for the passivation of exposed copper in a copper damascene structure are described. The composite layer consists of a passivation dielectric layer and an etch stop dielectric layer and is formed over the exposed copper prior to the deposit of an inter-metal or final passivating dielectric layer. Via holes are etched in the inter-metal or final passivating layer and the composite dielectric layer provides an etch stop function as well as passivation for the exposed copper conductor. A thin layer of passivation dielectric, such as silicon nitride, is formed directly over the exposed copper to passivate the copper. A thin layer of etch stop dielectric, such as silicon oxynitride, is then formed over the layer of passivation dielectric. The passivation dielectric is chosen for passivation properties and adhesion between the passivation dielectric and copper. The etch stop layer is chosen for etch stop properties.

Abstract: In one embodiment, the present invention relates to a method of removing fluorine from a gate conductor involving the steps of providing a semiconductor device containing a substrate, a gate insulator layer overlying a portion of the substrate, a gate conductor containing fluorine overlying the gate insulator layer, and a source and a drain region adjacent the gate insulator layer; and laser annealing the semiconductor device at an energy level sufficient to melt at least a portion of the gate conductor thereby inducing the removal of fluorine from the gate conductor. In another embodiment, the present invention relates to a method of making a transistor involving the steps of forming a gate conductor overlying a gate insulator layer, wherein the gate conductor and the gate insulator layer overlie a portion of a substrate, doping the substrate and gate conductor with BF.sub.2.sup.

Abstract: A process for removing copper from a boron doped, polished silicon wafer which contains copper on its polished surface and in its interior. In the process, the wafer is annealed at a temperature of at least about 75.degree. C. to increase the concentration of copper on the polished surface of the wafer and decrease the concentration of copper in the interior of the wafer. The polished surface of the annealed wafer is then cleaned to reduce the concentration of copper thereon. In addition, the annealing step is carried out at a temperature and a time such that the concentration of copper on the polished surface of the silicon will not increase by a factor of more than two upon storage of the annealed and cleaned wafer at room temperature for a period of 5 months.

Abstract: The present invention provides a method of forming a dielectric layer on a semiconductor wafer. The semiconductor wafer comprises a bottom dielectric layer and a plurality of metal lines each having a rectangular cross section positioned on the bottom dielectric layer. The method is performed in a high-density plasma chemical vapor deposition apparatus. A first deposition process at a first etching/deposition (E/D) ratio is performed to form a first dielectric layer with a predetermined thickness on the semiconductor wafer. The first dielectric layer covers the surface of the metal lines and forms a triangular ridge above each metal line. The upper side of each of the ridges has two slanted side-walls. Then, a second deposition process at a second E/D ratio is performed to form a second dielectric layer with a predetermined thickness on the semiconductor wafer with the second deposition process etching rate being near zero.

Abstract: There is provided a method of growing silicon monocrystal by Czochralski method where cusp field is applied to molten silicon, including the step of applying cusp field to molten silicon so that a center of the cusp field is situated at a depth of one-third or greater of an entire depth of the molten silicon, the depth being defined as a distance from a surface level of the molten silicon. The method makes it possible to eliminate growth slits in all regions in a growth direction of grown silicon monocrystal, and in addition, to accomplish uniform oxygen concentration profile where a difference in an oxygen concentration in a direction of a diameter of crystal is equal to or smaller than 5%. Furthermore, the method makes it possible to eliminate growth slits in all regions in a growth direction in a large-diameter silicon monocrystal, for instance, having a 40 cm-diameter.