Abstract: A test system for a DRAM module of an AMD system is configured to verify information write and read functions of an EEPROM included in the DRAM module. The test system includes at least one memory module slot and a processing unit. The at least one memory module slot is configured for insertion of the DRAM module. The DRAM module includes the EEPROM. After an operating system controlling the processing unit, an I2C operation register of the processing unit can access the DRAM module through an I2C bus, and can write test data to and read the test data from the EEPROM. When the test data does not have sample data, it can be replaced by serial presence detection information.

Abstract: This application provides a polar encoding method and apparatus. The method can include obtaining a basic sequence, where the basic sequence includes N0 subchannel numbers. The method can also include sequentially reading first subchannel numbers from the basic sequence, and sequentially reading 2m second subchannel numbers from the basic sequence starting from an Mth subchannel number based on the first subchannel number read each time; and adding q*N0 to each of the 2m second subchannel numbers to obtain 2m third subchannel numbers. Furthermore, the method can include constructing a polar code by using subchannels corresponding to the 2m third subchannel numbers as information bits. A polar code with another code length is constructed based on a sequence with a length of N0. A length of a polar code that needs to be stored is therefore reduced, which reduces complexity and is also easy to implement.

Abstract: Methods, systems, and devices for scrub rate control for a memory device are described. For example, during a scrub operation, a memory device may perform an error correction operation on data read from a memory array of the memory device. The memory device may determine a quantity of errors detected or corrected during the scrub operation and determine a condition of the memory array based on the quantity of errors. The memory device may indicate the determined condition of the memory array to a host device. In some cases, the memory device may perform scrub operations based on one or more condition of the memory array. For example, as a condition of the memory array deteriorates, the memory device may perform scrub operations at an increased rate.

Abstract: A method for repairing a processor. The processor comprises a plurality of processing units and an exchange comprising a plurality of exchange paths for transmitting data between the processing units. Each processing unit is connected to output data to a respective exchange path. An exchange path functional test of at least a portion of the exchange paths is carried out. Based on the exchange path functional test, it is identified that one or more of the exchange paths is defective, and the processing units connected to the one or more defective exchange paths is identified. The identified processing units are switched out of functional operation of the processor and switching in at least one repair processing unit connected to a non-defective exchange path for functional operation of the processor.

Abstract: Methods, systems, and devices for testing circuit for a memory device are described. An apparatus may include a memory system including contacts that route signals to different regions of the memory system. The apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. The apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. The first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. The first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.

Abstract: The present disclosure relates to techniques for forward error correction and packet padding in radio transmission, e.g. WiFi communication schemes such as IEEE 802.11ax and 802.11be. In particular, the disclosure relates to a communication device configured to: transmit and/or receive a data frame based on a set of pre&post-Forward Error Correction (pre&post-FEC) parameters and a set of packet extension (PE) parameters, wherein the set of pre&post-FEC parameters is based on an extension of a set of pre&post-FEC parameters defined for a second radio transmission technology with respect to a size of resource units (RUS) supported by a first radio transmission technology, wherein the set of pre&post-FEC parameters is based on a combination of RUs that is supported by the first radio transmission technology, and wherein the set of PE parameters is based on an extension of a set of PE parameters defined for the second radio transmission technology.

Abstract: A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends an error injection access command signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of the error injection access command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, with controlling a memory cell array of flash memory device generating failure errors.

Abstract: A method and an apparatus for encoding and for decoding a polar code to reduce complexity and improve speed. For encoding, information bits are obtained, an original kernel matrix is adjusted to construct one or more kernel matrices, an appropriate target kernel matrix is selected from the one or more kernel matrices, and polar encoding is performed on the information bits based on the target kernel matrix. For decoding, a to-be-decoded sequence is obtained, and the to-be-decoded sequence is decoded based on a plurality of trellises, where intermediate results obtained in different decoding stages may be reused. For example, in a (t+i)th stage of decoding, an intermediate result obtained in a tth stage of decoding is reused.

Abstract: A method of testing a three dimensional (3D) memory cell array includes writing data to each layer of memory cells in the 3D memory cell array, simultaneously performing a read operation of each memory cell in at least a first pillar of the 3D memory cell array, determining whether a memory cell in the 3D memory cell array has failed in response to the read operation, and replacing at least one failed memory cell in the 3D memory cell array with a spare memory cell in response to determining that the memory cell in the 3D memory cell array has failed. The first pillar includes memory cells on each corresponding layer of the 3D memory cell array.

Abstract: Embodiments herein relate to e.g., a method performed by a network node for handling a received signal in a communication network. The network node includes at least two processing cores connected via a bus system for handling the received signal. The network node receives input bits associated with the received signal and permutes the received input bits into input bits of permuted order taking at least number of processing cores into account. The network node further decodes the input bits of the permuted order and re-permutes the decoded input bits into original order.

Abstract: A method for reducing observed processing latency in networked communication, the method comprising: receiving a first portion of data, the data consisting of the first portion and a second portion; initializing data processing on the data after receiving the first portion of data and before receiving the second portion of the data; receiving the second portion of the data, the second portion of the data including error-detection code; performing error detection on the data based on the error-detection code; in response to the error detection indicating that the data is valid, finalizing data processing on the data and committing a data-processing result; and in response to the error detection indicating that the data is invalid, performing an error-correction process.

Abstract: A decoding method includes: decoding first to-be-decoded information based on a first decoder to obtain a first decoding result that includes first soft information or a first hard output; and correcting the first decoding result based on a first correction model to obtain a corrected first decoding result of the first to-be-decoded information. The first correction model is obtained through training based on training data that includes a training decoding result and a corrected training decoding result. The training decoding result is a decoding result obtained after the first decoder decodes training to-be-decoded information, and the corrected training decoding result is a corrected decoding result corresponding to the training decoding result. In this way, after a decoder performs decoding, a decoding result can be corrected based on a correction model.

Abstract: A plurality of failure domains are communicatively coupled to each other via a network, and each of the plurality of failure domains is coupled to one or more storage devices. A failure resilient stripe is distributed across the plurality of storage devices, such that two or more blocks of the failure resilient stripe are located in each failure domain.

Abstract: A memory testing device uses a master control unit to concurrently operate multiple, intelligent, slave control units (SCUs). SCUs have one or more processing unit(s) (i.e. Finite State Machines, micro controllers, processors) capable of processing one or more firmware with or without operating system (i.e. bare-metal, embedded OS, RTOS (real time operating system)) to perform a series of task defined by firmware(s) for testing volatile and/or non-volatile memory devices connected into one or more DUT devices plus SCU has capability of having operating system and install and run host applications locally within each SCU units to mimic host applications environments along with performing regular memory testing.

Abstract: The performance of a microelectronic circuit can be configured by making an operating parameter assume an operating parameter value. An operating method comprises selectively setting the microelectronic circuit into a test mode that differs from a normal operating mode of the microelectronic circuit, and utilizing said test mode to input test input signals consisting of test input values into one or more adaptive processing paths within the microelectronic circuit. An adaptive processing path comprises processing logic and register circuits configured to produce output values from input values input to them. The performance of such an adaptive processing path can be configured by making an operating parameter assume an operating parameter value.

Abstract: A data transmission circuit and a data transmission method applied to the data transmission circuit are provided. The data transmission circuit includes: a data strobe module, connected to multiple memory blocks, connected to a low-bit data port through a first group of data buses, and connected to a high-bit data port through a second group of data buses, where each group of data buses include an odd data line and an even data line; and an error correction module, where each group of the data buses are provided with the error correction module, the error correction module is provided on the odd data line or the even data line, and the error correction module is configured to perform error correction on data written through the low-bit data port or the high-bit data port.

Abstract: A device capable of operating in a wireless communication environment. The device may be configured to determine a plurality of control signaling bits. The device may determine a plurality of cyclic redundancy check (CRC) bits based on the plurality of control signaling bits. The device may apply a channel coding scheme to the plurality of control signaling bits and the plurality of CRC bits. The plurality of CRC bits may be distributed among the plurality of control signaling bits prior to applying the channel coding scheme. The device may transmit the channel coded plurality of control signaling bits and CRC bits.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums which provide for an enhanced decoding system that utilizes a variable sequence decoding to demultiplex data streams at a receiver. For example, the receiver may utilize an erasures decoding when the number of unknown bits, such as dissimilar transmitted bits (e.g., ‘1 0’ or ‘0 1’), is below a threshold (which may be the Hamming distance D?1). Otherwise, if the number of dissimilar transmitted bits is above the threshold, a list decoding is utilized. If the list decoding does not produce a single result, but instead produces multiple possible results, selection logic may be employed. The selection logic may utilize an errors and erasures decoding of the possible results, a media decoding of the possible results, and/or the like.

Abstract: A technique protects user data within a storage system. The technique involves, in response to a request signal that directs the storage system to store the user data, generating first parity and second parity based on the user data. The technique further involves storing the first parity and the user data in a data uber of the storage system, the data uber providing redundant array of independent disks (RAID) protection. The technique further involves storing the second parity in designated free storage of the storage system, the designated free storage being separate from the data uber.

Abstract: A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.