Abstract: The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

Abstract: A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: There is provided a semiconductor apparatus including a memory controller; a CPU; a high-speed communication controller; a memory operation terminal group that includes a plurality of memory operation terminals for inputting a first signal propagating between an external memory group and the memory controller; a high-speed communication terminal group that includes a plurality of high-speed communication terminals for inputting a second signal to the high-speed communication controller; an inspection terminal group that includes a plurality of inspection terminals for acquiring information from the CPU and performing debugging; and a terminal mounting surface at which the memory operation terminal group, the high-speed communication terminal group, and the inspection terminal group are provided, in which at the terminal mounting surface, a first inspection terminal among the plurality of inspection terminals is located between the memory operation terminal group and the high-speed communication terminal group

Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.

Abstract: An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO.

Abstract: To provide a semiconductor device having a monitoring function with a higher degree of freedom. The semiconductor device includes: a function part that executes a predetermined process triggered according to an activation signal sent from an external device and outputs a completion signal after the predetermined process is completed; a first clocking part that monitors a first abnormality in the predetermined process based on the activation signal and the completion signal; and a branch part pair including a first branch part and a second branch part, wherein the first branch part branches the activation signal and then sends the branched activation signal to the function part and the first clocking part, and the second branch part branches the completion signal and then sends the branched completion signal to the first clocking part and the external device.

Abstract: A method for dynamically handling the failure of the static random-access memory (SRAM) dynamic failure handling system using a cyclic redundancy check (CRC) includes obtaining a write data; determining a write address; storing the write data at the write address of a frame memory which is composed of the SRAM and includes a real address area and a spare address area which are distinguished from each other; storing, in response to the write address, a write cyclic redundancy check (CRC) generated by performing a CRC calculation on the write data; determining a read address; reading a read data from the read address of the frame memory; determining whether, based on the A CRC remainder W_CRC corresponding to the read address and the read data, a CRC error occurs, and generating an error flag when the CRC error occurs; determining a fault address based on the error flag; and mapping the fault address to one of non-fault spare addresses of the spare address area when the fault address is an address of the real a

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform parity-permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern, wherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame.

Abstract: A memory device to estimate a bit error count of data retrievable from a group of memory cells. For example, the memory device has a group of memory cells programmed to store a predetermined number of bits per memory cells to be read at a plurality of first voltages. The memory device determines a plurality of calibrated read voltages corresponding to the plurality of first voltages respectively, based on first signal and noise characteristics of the group of memory cells. The first signal and noise characteristics are used to compute second signal and noise characteristics of the group of memory cells for the calibrated read voltages. The second signal and noise characteristics are used in an empirical formula to compute an estimate of the bit error count of data retrievable from the group of memory cells using the calibrated read voltages.

Abstract: A storage device may detect errors during data transfer. Upon detection of one or more data transfer errors, for example, the storage device can begin to scan pages within a plurality of memory devices for uncorrectable error correction codes. Once scanned, a range of pages within the plurality of memory devices with uncorrectable error correction codes associated with a write abort error may be determined. The stage of multi-pass programming achieved on each page within that range is then established. Once calculated, the previously aborted multi-pass programming of each page within the range of pages can continue until completion. Upon completion, normal operations may continue without discarding physical data location.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to interleave the parity bits and group-wise interleave a plurality of parity bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern to perform parity permutation; a puncturer configured to puncture at least some of the group-wise interleaved parity bit groups; and an additional parity generator configured to select at least some of the punctured parity bit groups to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern.

Abstract: A monitoring circuit and a method for function monitoring is disclosed where the device includes the input being connected with a first subassembly that detects a frequency range of the status signal, with the first subassembly being connected with a second subassembly to implement a logical signal combination. The second subassembly is connected with a third subassembly generating a delayed output signal. The method compares a frequency fsw of the status signal with a lower first cutoff frequency f1 and an upper second cutoff frequency f2. When the frequency fsw of the status signal is located within the predetermined frequency range, the functional reliability signal is provided with a first voltage level, and when the frequency fsw of the status signal is located outside of the predetermined frequency range, the functional reliability signal is provided with a second voltage level that is different from the first voltage level.

Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

Abstract: Consistent with a further aspect of the present disclosure, previously encoded data is stored in a memory, and an encoder accesses both input data and previously encoded data to generate new encoded data or a new codeword. Each codeword is stored in a row of the memory, and with each newly generated codeword, each previously stored code word is shifted to an adjacent row of the memory. In one example, the memory is delineated as a plurality of blocks including rows and columns of bits. When generating a new code word, randomly selected columns of bits in the memory are read from randomly selected blocks of the memory and supplied to the encoder. In this manner the number of times the memory is access is reduced and power consumption is reduced.

Abstract: A system includes a test access port (TAP) configured to provide internal joint test action group (IJTAG) access to one or more test data registry (TDR). The system further includes a plurality of hierarchical electronic components, wherein each hierarchical electronic component includes a de-asserted segment inserted bit (D-SIB) register, an asserted segment inserted bit (A-SIB) register, and a TDR associated with the D-SIB register. Each D-SIB register is configured to prevent access to its associated TDR when a reset signal is asserted and each A-SIB register is configured to provide access to its subsequent A-SIB register or D-SIB register coupled thereto when the reset signal is asserted.

Abstract: A communication method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The method and apparatus for polar encoding and rate-matching are disclosed.

Abstract: A quasi-cyclic LDPC coding and decoding method and apparatus, and an LDPC coder and decoder. The method includes: determining from a mother basis matrix set a basis matrix used for low density parity check (LDPC) coding (S202), wherein the basis matrix used for LDPC coding includes a first-type element and a second-type element, the first-type element corresponds to an all-zero square matrix, the second-type element corresponds to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and dimensions of the all-zero square matrix and the unit matrix are equal; and performing LDPC coding on an information sequence to be coded according to the basis matrix used for LDPC coding, and/or performing LDPC decoding on a data sequence to be decoded according to the basis matrix used for LDPC coding (S204).

Abstract: A storage device includes: a memory; and a processor configured to, at the time of writing data into the memory, generate a first check code common to a plurality of types of error correction codes from the data on the basis of a correlation relationship between the plurality of types of error correction codes, add the first check code to the data and write the data into the memory, convert the first check code into a second check code based on any one of the plurality of types of error correction codes at the time of reading the data from the memory, and perform error correction by using the second check code.