Abstract: A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.
Abstract: Embodiments provide a scheme for parametric PV-level modeling and an optimal read threshold voltage estimation in a memory system. A controller performs read operations on cells using read threshold voltages; generates CMF samples based on the read operations; and receives first and second CDF values, which correspond to CMF samples, each CDF value representing a skew normal distribution. The controller estimates first and second probability distribution parameter sets corresponding to the first and second CDF values, respectively; determines first and second PDF values using the first and second probability distribution parameter sets, respectively; and estimates, as an optimal read threshold voltage, a read threshold voltage corresponding to a cross-point of the first and second PDF values.
Abstract: A method for detecting and isolating defective memory plane(s) of a non-volatile memory structure during a program verify operation, comprising: initiating, for each plane, a word line verify voltage level scan with a bit scan pass fail criterion and at a starting voltage located within an intended program threshold voltage distribution curve, incrementally decreasing the word line verify voltage by a predetermined offset until a specific condition of the scan is obtained, and storing the voltage at which the specific condition of the scan is obtained, wherein the stored voltage represents a voltage of an upper tail portion of an actual programmed threshold voltage distribution curve of the plane. The stored voltages of all of the memory planes of the structure are compared to determine which plane corresponds to the lowest stored voltage. A “fail” status is applied to the plane corresponding to the lowest stored voltage.
Abstract: A setup time and hold time detection system including a monitoring unit and a processing unit. The monitoring unit is configured to detect multiple setup times and multiple hold times of multiple test circuits through a source clock signal. The processing unit is configured to record multiple setup times and multiple hold times as multiple detection data. The processing unit is further configured to select a first part of the detection data as multiple first detection data to establish an estimation model. The processing unit is further configured to select a second part of the detection data as multiple second detection data, and compare the second detection data and multiple estimation results generated by the estimation model to obtain an error value of the estimation model.
Abstract: Memory devices are disclosed. A memory device may include a number of column planes, and at least one circuit. The at least one circuit may be configured to receive test result data for a column address for each column plane of the number of column planes of the memory array. The at least one circuit may also be configured to convert the test result data to a first result responsive to only one bit of a number of bits of the number of column planes failing a test for the column address. Further, the at least one circuit may be configured to convert the test result data to a second result responsive to only one column plane failing the test for the column address and more than one bit of the one column plane being defective. Methods of testing a memory device, and electronic systems are also disclosed.
Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter.
June 4, 2020
Date of Patent:
November 22, 2022
Huawei Technologies, Co., Ltd.
Huazi Zhang, Jiajie Tong, Rong Li, Jun Wang, Wen Tong, Yiqun Ge, Xiaocheng Liu
Abstract: A semiconductor memory device included in each of a plurality of chips which are divided by a scribe lane and formed on an upper surface of a wafer, includes a memory core and a built-in self test (BIST) circuit. The memory core includes a memory cell array that stores data and a data input/output circuit connected to a data input/output pad. The BIST circuit is connected to a test pad that is separate from the data input/output pad. The BIST circuit generates test pattern data including first parallel bits based on commands and addresses received from an external automatic test equipment (ATE) during a wafer level test process performed on the semiconductor memory device. The BIST circuit tests the memory core by applying the test pattern data to the memory cell array through the data input/output circuit.
Abstract: A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.
Abstract: A storage device having improved data recovery performance includes a memory device including a first storage region and a second storage region, and a memory controller that controls the memory device. Before performing a write operation in the first storage region, the memory controller may backup data previously stored in the first storage region, based on a fail probability of the write operation to be performed in the first storage region. If the write operation fails, the previously-stored data may be recovered from where it was backed up.
Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.
September 10, 2020
Date of Patent:
November 1, 2022
Micron Technology, Inc.
Harish Reddy Singidi, Xiangang Luo, Preston Allen Thomson, Michael G. McNeeley
Abstract: A storage client needs to store to-be-written data into a distributed storage system, and storage nodes corresponding to a first data unit assigned for the to-be-written data by a management server are only some nodes in a storage node group. When receiving a status of the first data unit returned by the management server, the storage client may determine quantities of data blocks and parity blocks needing to be generated during EC coding on the to-be-written data. The storage client stores the generated data blocks and parity blocks into some storage nodes designated by the management server in a partition where the first data unit is located. Accordingly, dynamic adjustment of an EC redundancy ratio is implemented, and the management server may exclude some nodes in the partition from a storage range of the to-be-written data based on a requirement, thereby reducing a data storage IO amount.
Abstract: A Magnetoresistive Random Access Memory (MRAM) device is tested using a high repetition test that detects one or more low-likelihood failures, such as a failure to properly switch between a high or low resistive state. A series of write and read operations are performed for a large number of test cycles at high frequency. A first tier measurement is used to determine if a switching failure occurred, e.g. by comparing the read signal to target level(s) after each operation. When a switching failure event is detected, a second tier measurement is used to measure and store switching performance parameters, for example, the value of the read signal, while the MRAM device is in a failure state. The high frequency testing may be paused during the second tier measurements. Additional performance parameters may be measured during the second tier measurements.
Abstract: A method includes encoding an input data stream to generate an encoded input data pattern, transmitting the encoded input data pattern to a programmed automata processor, and searching the encoded input data pattern via the programmed automata processor to identify an identifiable data pattern within the encoded input data pattern as a data pattern search.
Abstract: A controller of a memory system performs a soft decoding without additional reads. The controller applies each of read voltages to cells to obtain a corresponding cell count and corresponding data, stores the obtained data, and processes the stored data. The controller determines a set of parameters, based on (i) the read voltages, (ii) cell counts corresponding to the read voltages and (iii) a non-negative regularization parameter. The controller estimates an optimal read voltage based on the set of parameters, generates log-likelihood ratio (LLR) values using the processed data and the optimal read voltage and performs soft decoding using the LLR values.
Abstract: Methods, systems, and devices for programming anti-fuses are described. An apparatus may include a repair array including elements for replacing faulty elements in a memory array and may further include an array of anti-fuses for indicating which, if any, elements of the memory array are being replaced by elements within the repair array. The array of anti-fuses may indicate an address of an element of the memory array being replaced by an element within the repair array. The array of anti-fuses may indicate an enablement or disablement of the element within the repair array indicating whether the element within the repair array is enabled to replace the element of the memory array. The array of anti-fuses may include anti-fuses with lower reliability and anti-fuses with higher reliability. An anti-fuse associated with the enabling of the element within the repair array may include an anti-fuse having the higher reliability.
Abstract: An association with a system timing at the time of transmission is secured without changing a display timing in text information of a subtitle, and a reception side displays the subtitle at an appropriate timing. A packet in which a document of the text information of the subtitle having display timing information is included in a payload is generated and transmitted in synchronization with a sample period. A header of the packet includes a time stamp on a first time axis indicating a start time of the corresponding sample period. The payload of the packet further includes reference time information of a second time axis regarding the display timing associated with the start time of the corresponding sample period.
Abstract: A repair method of a memory includes dividing a plurality of general bits into a plurality of first groups and dividing a plurality of redundancy bits into a plurality of second groups. When one of the plurality of first groups has a defective bit, one of the plurality of second groups is selected to replace the first group which has the defective bit. Because the repair method uses a group as a repair unit, a repair circuit is simpler and smaller and a processing speed of the repair circuit is faster.
Abstract: A decoding method includes inputting coded data, and decoding the coded data to obtain decoded data. The coded data are generated by using an encoding process at an encoding apparatus, and the encoding process includes: (i) repeatedly-selecting and collecting first packets included in the decoded data to generate at least one second packet; (ii) dividing at least one third packet included in the decoded data into fourth packets; and (iii) allocating fifth packets included in the decoded data to respective sixth packets without collecting the first packets or dividing the at least one third packet, and performing an error correcting encoding on the at least one second packet, the fourth packets, and the sixth packets in accordance with a coding rate selected from a plurality of coding rates to generate parity data.
April 29, 2020
Date of Patent:
October 4, 2022
Panasonic Intellectual Property Corporation of America
Abstract: The disclosed subject matter is directed towards scheduling and Hybrid Automatic Repeat Request (HARQ) operations by which nodes in a three party communication system can communicate. To schedule a data transmission from a transmitter node to receiver node(s), a local manager/scheduler node sends common downlink control information to the transmitter and receiver nodes. Via a scheduling request, the transmitting node can request the scheduling of the data transmission by the local manager node. The technology facilitates unicast and broadcast/multicast data transmissions; for a unicast data transmission, the scheduling request identifies the receiving node. The transmitting node can explicitly acknowledge reception of the downlink control information to the local manager node, or the local manager node can detect the data transmission, when it occurs, as an implicit acknowledgment that the common downlink control information was successfully received.
February 3, 2021
Date of Patent:
September 20, 2022
AT&T INTELLECTUAL PROPERTY I, L.P.
Ralf Bendlin, Xiaoyi Wang, Andrew Thornburg, Thomas Novlan
Abstract: The present disclosure relates to an apparatus comprising a non-volatile memory architecture configured to be coupled to a System-on-Chip (SoC) device. The non-volatile memory device coupled to the SoC having a structurally independent structure linked to the SoC includes a plurality of sub arrays forming a matrix of memory cells with associated decoding and sensing circuitry, sense amplifiers coupled to a corresponding sub array, a data buffer comprising a plurality of JTAG cells coupled to outputs of the sense amplifiers; and a scan-chain connecting together the JTAG cells of the data buffer.