Patents Examined by Guerrier Merant
  • Patent number: 11637568
    Abstract: A quasi-cyclic LDPC coding and decoding method and apparatus, and an LDPC coder and decoder. The method includes: determining from a mother basis matrix set a basis matrix used for low density parity check (LDPC) coding (S202), wherein the basis matrix used for LDPC coding includes a first-type element and a second-type element, the first-type element corresponds to an all-zero square matrix, the second-type element corresponds to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and dimensions of the all-zero square matrix and the unit matrix are equal; and performing LDPC coding on an information sequence to be coded according to the basis matrix used for LDPC coding, and/or performing LDPC decoding on a data sequence to be decoded according to the basis matrix used for LDPC coding (S204).
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: April 25, 2023
    Assignee: ZTE Corporation
    Inventors: Liguang Li, Jun Xu, Jin Xu
  • Patent number: 11637653
    Abstract: A communication method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The method and apparatus for polar encoding and rate-matching are disclosed.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: April 25, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Jang, Seokki Ahn, Seho Myung, Hongsil Jeong, Kyungjoong Kim, Jaeyoel Kim
  • Patent number: 11637655
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: April 25, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-joong Kim, Se-ho Myung, Daniel Ansorregui Lobete, Belkacem Mouhouche
  • Patent number: 11631469
    Abstract: An integrated circuit includes a test control circuit, a driving circuit, and a test detection circuit. The test control circuit generates a test command signal and a test address signal corresponding to a test operation. The driving circuit performs the test operation by utilizing a test internal voltage, which is generated based on the test command signal. The test detection circuit compares the test address signal with target address information to output the test internal voltage.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: April 18, 2023
    Assignee: SK hynix Inc.
    Inventor: Seung Hyun Chung
  • Patent number: 11632132
    Abstract: A processing device in a memory system receives a request to read data from a memory device. In response to receiving the request, the processing device performs an iterative error correction process on the data, wherein at least one iteration after a first iteration in the error correction process uses a criterion that is based at least partially on a previous iteration or partial iteration, and wherein performing the iterative error correction process comprises flipping any bits in the data having an associated number of unsatisfied parity check equations that satisfies a threshold criterion associated with the previous iteration.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: April 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Eyal En Gad, Zhengang Chen, Sivagnanam Parthasarathy, Yoav Weinberg
  • Patent number: 11632136
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: April 18, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11632130
    Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: April 18, 2023
    Assignee: Intel Corporation
    Inventors: Zuoguo Wu, Debendra Das Sharma, Md. Mohiuddin Mazumder, Subas Bastola, Kai Xiao
  • Patent number: 11626186
    Abstract: An apparatus includes a boot-up control circuit configured to, when a first boot-up operation is performed, latch first fuse data by receiving the first fuse data and fuse information from a fuse circuit and configured to, when a second boot-up operation is performed, latch second fuse data by receiving the second fuse data from the fuse circuit based on the fuse information; and a rupture control circuit configured to store a failure address as the second fuse data by rupturing the fuse circuit based on the fuse information.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: April 11, 2023
    Assignee: SK hynix Inc.
    Inventors: Dong Beom Lee, Hyeong Soo Jeong
  • Patent number: 11620241
    Abstract: Methods, systems, and devices for dynamically configuring transmission lines of a bus between two electronic devices (e.g., a controller and memory device) are described. A first device may determine a quantity of bits (e.g., data bits, control bits) to be communicated with a second device over a data bus. The first device may partition the data bus into a first set of transmission lines (e.g., based on the quantity of data bits) and a second set of transmission lines (e.g., based on the quantity of control bits). The first device may communicate the quantity of data bits over the first set of transmission lines and communicate the quantity of control bits over the second set of transmission lines. In some cases, the first device may repartition the data bus based on different quantities of data bits and control bits to be communicated with the second device at a different time.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: April 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michael Dieter Richter, Thomas Hein, Martin Brox, Peter Mayer, Wolfgang Anton Spirkl
  • Patent number: 11620183
    Abstract: A method for reducing observed processing latency in networked communication, the method comprising: receiving a first portion of data, the data consisting of the first portion and a second portion; initializing data processing on the data after receiving the first portion of data and before receiving the second portion of the data; receiving the second portion of the data, the second portion of the data including error-detection code; performing error detection on the data based on the error-detection code; in response to the error detection indicating that the data is valid, finalizing data processing on the data and committing a data-processing result; and in response to the error detection indicating that the data is invalid, performing an error-correction process.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: April 4, 2023
    Inventor: Johnny Yau
  • Patent number: 11615003
    Abstract: In some implementations, the present disclosure relates to a method. The method includes obtaining a set of weights for a neural network comprising a plurality of nodes and a plurality of connections between the plurality of nodes. The method also includes identifying a first subset of weights and a second subset of weights based on the set of weights. The first subset of weights comprises weights that used by the neural network. The second subset of weights comprises weights that are prunable. The method further includes storing the first subset of weights in a first portion of a memory. A first error correction code is used for the first portion of the memory. The method further includes storing the second subset of weights in a second portion of the memory. A second error correction code is used for the second portion of the memory. The second error correction code is weaker than the first error correction code.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: March 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chao Sun, Yan Li, Dejan Vucinic
  • Patent number: 11611357
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: March 21, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11605412
    Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Richard E. Fackenthal, Daniele Vimercati, Duane R. Mills
  • Patent number: 11595057
    Abstract: Systems and methods are provided for reducing error in data compression and decompression when data is transmitted over low bandwidth communication links, such as satellite links. Embodiments of the present disclosure provide systems and methods for variable block size compression for gridded data, efficiently storing null values in gridded data, and eliminating growth of error in compressed time series data.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: February 28, 2023
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventor: John T. Sample
  • Patent number: 11595058
    Abstract: Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: February 28, 2023
    Assignee: Seagate Technology LLC
    Inventors: Naveen Kumar, Shuhei Tanakamaru, Erich Franz Haratsch
  • Patent number: 11595151
    Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform by group-wise interleaving a plurality of bit groups configuring the parity bits based on a group-wise interleaving pattern comprising a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: February 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-Joong Kim, Se-ho Myung
  • Patent number: 11579776
    Abstract: In one aspect, an apparatus includes a memory repair controller coupled to a memory. The memory repair controller may be configured to provide repair information to cause the memory to disable one or more faulty locations in the memory, and the memory repair controller can be disabled after providing the repair information.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: February 14, 2023
    Assignee: Silicon Laboratories Inc.
    Inventors: Mudit Srivastava, Anil Shirwaikar, Yu Zhou
  • Patent number: 11579192
    Abstract: An error rate measuring apparatus includes a data transmission unit that transmits a test signal of a known pattern and a parameter value defined by a communication standard to a device under test, and a bit error measurement unit that measures a bit error of a signal transmitted from the device under test. The data transmission unit sequentially changes the parameter value and transmits the parameter value to the device under test. The bit error measurement unit measures a bit error of a signal transmitted from the device under test corresponding to the parameter value. The error rate measuring apparatus further includes a discrimination unit that discriminates a parameter value at which the number of bit errors is the least in a measurement result of the bit error measurement unit, as an optimum value of emphasis of an output waveform of the device under test.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 14, 2023
    Assignee: ANRITSU CORPORATION
    Inventors: Hisao Kidokoro, Hiroyuki Inaba
  • Patent number: 11567130
    Abstract: An integrated circuit device may include core circuitry, and a set of external interface buffer circuits coupled to the core circuitry. To improve test time and accuracy, as well as to simplify test procedures during voltage testing of the set of external interface buffer circuits, the integrated circuit device may include a test circuit and a combinational logic circuit coupled to the set of external interface buffer circuits. The combinational logic circuit is configured to combine a logic level of each of the external interface buffer circuits into a test signal, and the test circuit is configured to execute a voltage test on the set of external interface buffer circuits based on a logic level of the test signal.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: January 31, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Dan Trock, Alon Postavski, Etai Wagner, Victor David Romanov
  • Patent number: 11568954
    Abstract: A memory apparatus and method of operation is provided. The apparatus has blocks each including non-volatile storage elements. Each of the non-volatile storage elements stores a threshold voltage representative of an element data. The apparatus also includes one or more managing circuits configured to erase at least one of the blocks in an erase operation and program the element data in a program operation. The one or more managing circuits are also configured to proactively identify ones of the blocks as potential bad blocks and selectively apply stress to the ones of the blocks identified as the potential bad blocks and determine whether the potential bad blocks should be retired from the erase and program operations and put in a grown bad block pool or released to a normal block pool used for the erase and program operations based on a judgment after selectively applying the stress.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: January 31, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Liang Li, Ming Wang