Abstract: A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, the fail detecting method including: counting, by the memory controller, the number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller, when the number of erases reaches a reference value; applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value; detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; and determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.

Abstract: A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

Abstract: Methods, systems, and devices for forwarding a code word address are described. A memory subsystem, for example, may configure a code word including user data as a forwarded code word when the code word becomes unreliable or invalid close to or beyond an error recovery capability of the memory subsystem. The memory subsystem may configure the forwarded code word using a forwarded code word format and structure, which may include a bit field in the forwarded code word to indicate a code word condition and to store a quantity of duplicates of a forwarding address. When the memory subsystem receives a code word, the memory system may determine the code word as a forwarded code word such that the memory system may determine a forwarding address (e.g., from the code word). The memory subsystem may then use the forwarding address to access user data.

Abstract: A convolutional code rate matching method and a communication apparatus are provided. A puncturing pattern of a second codeword at a second code rate is obtained based on a puncturing pattern of a first codeword at a first code rate. A second puncturing location set of the second codeword is a subset of a first puncturing location set of the first codeword. When a transmit device decreases a code rate from the first code rate to the second code rate, a redundant bit is sent at a location of a complementary set of the second puncturing location set relative to the first puncturing location set. Compared with the first puncturing location set, the second puncturing location set may obtain more incremental redundant bits, to decrease a channel encoding rate. This can improve decoding performance of a convolutional code.

Abstract: A method and a decoder for receiving a message encoded in Turbo Codes and modulated for transmission as an analog signal includes: (a) demodulating the analog signal to recover the Turbo Codes; and (b) decoding the Turbo Codes to recover the message using an iterative Turbo Code decoder, wherein the decoding includes performing an error detection after a predetermined number of iterations of the Turbo Code decoder to determine whether or not an error has occurred during the transmission. The predetermined number of iterations may be, for example, two. Depending on the result of the error detection, the decoding may stop, a request for retransmission of the message may be sent, or further iterations of decoding in the Turbo Code decoder may be carried out.

Abstract: The present disclosure provides a memory device test method, apparatus, and system, a medium, and an electronic device. The memory device test method includes: determining an operation path according to position coordinates of a target test platform and current position coordinates of a memory device; setting a movable apparatus according to the operation path, such that the movable apparatus moves the memory device into the target test platform according to the operation path; controlling the target test platform to test the memory device according to a target test program; and monitoring a test result of the memory device in real time, and storing the test result of the memory device into a database.

Abstract: A memory test method, a memory test apparatus, a device and a storage medium are provided. The memory test method includes: obtaining a central processing unit (CPU) accessible space of a memory to-be-tested; obtaining a graphics processing unit (GPU) accessible space of the memory to-be-tested; and driving a CPU to run a test program based on the accessible space of the CPU, to access the memory to-be-tested through a bus of memory to-be-tested, when the CPU runs the test program, the CPU controls a GPU to access the memory to-be-tested based on the accessible space of the GPU through the bus of memory to-be-tested.

Abstract: A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.

Abstract: The invention relates to a method, an apparatus and a non-transitory computer-readable storage medium for debugging a solid-state disk (SSD) device. The method is performed by a processing unit of a single-board personal computer (PC) when loading and executing a function of a runtime library, to include: receiving a request to drive a General-Purpose Input/Output (GPIO) interface (I/F), which includes a parameter required for completing a Joint Test Action Group (JTAG) command; issuing a first hardware instruction to the GPIO I/F to set a register corresponding to a GPIO test data input (TDI) pin according to the parameter carried in the request for emulating to issue the JTAG command to a solid-state disk (SSD) device, wherein the single-board PC is coupled to the SSD device through the GPIO I/F; issuing a second hardware instruction to the GPIO I/F to read a value of the register corresponding to the GPIO TDI pin; and replying with a completion message in response to the request.

Abstract: According to one embodiment, a memory controller controls a plurality of non-volatile memory chips. The memory controller includes a memory that stores first data and a processing unit that processes the first data stored in the memory. During a write operation, the processing unit generates second data including the first data and additional data corresponding to the first data, changes the bit order of the second data based on information indicating the state of the write destination of the second data, and writes the second data having the changed bit order to the plurality of non-volatile memory chips. During a read operation, the processing unit reads the second data having the changed bit order from the plurality of non-volatile memory chips and revert the bit order of the read second data to the original state based on the information.

Abstract: Apparatuses and techniques are presented for detecting bit line open circuits and short circuits in a memory device in which a memory die is inverted and bonded to a control die. In one approach, the control die comprises a set of bit lines which are connected to a set of bit lines of the memory die, and the set of bit lines of the control die comprise ground transistors, e.g., transistors connected to a ground node. Ground transistors of even-numbered bit lines may be commonly controlled, while ground transistors of odd-numbered bit lines are commonly controlled. The ground transistors may be controlled to detect open circuits and short circuits in the bit lines of the control die and the memory die. A laser scanning technique can also be used to determine a physical location of a defect of a bit line.

Abstract: A method for uplink (UL) wireless backhaul communication at a wireless backhaul remote unit in a radio access network comprising receiving a configuration for radio frames and a transmission schedule through a downlink (DL) physical layer broadcast channel, wherein the transmission schedule comprises a transmission allocation for the remote unit, generating a UL data frame, wherein generating the UL data frame comprises performing forward error correction (FEC) encoding on a data bit stream to generate a plurality of FEC codewords, wherein performing the FEC encoding comprises performing Reed Solomon (RS) encoding on the data bit stream to generate a plurality of RS codewords, performing byte interleaving on the RS codewords, and performing Turbo encoding on the byte interleaved RS codewords to generate one or more Turbo codewords, wherein each Turbo codeword is encoded from more than one RS codeword, and transmitting the UL data frame according to the transmission allocation.

Abstract: There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes: a plurality of memory blocks each including a plurality of select transistors and a plurality of memory cells; a peripheral circuit for performing a general operation including a program operation, a read operation, and an erase operation on the plurality of memory blocks; and a control logic for controlling the peripheral circuit to operate in a heating mode in which the peripheral circuit applies heat to the plurality of memory blocks.

Abstract: A memory system includes a plurality of memory cells each storing multiple bits and a memory controller having a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host to generate first raw data of a first page and second raw data of a second page adjacent to the first page. The memory controller is further configured to perform a hard decision (HD) decoding on the first raw data to generate first decoded data. The processor is configured to apply the first decoded data and the second raw data as input features to a machine learning algorithm to generate reliability information. The memory controller is further configured to perform a HD decoding on the second raw data using the reliability information to generate second decoded data.

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

Abstract: Provided is a non-volatile storage system that performs error correction processing at high speed while ensuring error correction capability. When error correction decoding processing using data read first with hard-decision decoding processing has failed, a non-volatile storage device 2 reads data on the same page again, performs diversity synthesis processing on the readout data for the first time and the readout data for the second time on the same page as one for the first time, and then performs error correction processing using data after diversity synthesis processing.

Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

Abstract: An association with a system timing at the time of transmission is secured without changing a display timing in text information of a subtitle, and a reception side displays the subtitle at an appropriate timing. A packet in which a document of the text information of the subtitle having display timing information is included in a payload is generated and transmitted in synchronization with a sample period. A header of the packet includes a time stamp on a first time axis indicating a start time of the corresponding sample period. The payload of the packet further includes reference time information of a second time axis regarding the display timing associated with the start time of the corresponding sample period.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: A method of testing a three dimensional (3D) memory cell array includes writing data to each layer of memory cells in the 3D memory cell array, simultaneously performing a read operation of each memory cell in at least a first pillar of the 3D memory cell array, determining whether a memory cell in the 3D memory cell array has failed in response to the read operation, and replacing at least one failed memory cell in the 3D memory cell array with a spare memory cell in response to determining that the memory cell in the 3D memory cell array has failed. The first pillar includes memory cells on each corresponding layer of the 3D memory cell array.